Patents by Inventor Yong-Bin Lee

Yong-Bin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240349466
    Abstract: A converter comprises: a housing; an electronic component disposed in the housing; and heat dissipation fins protruding from the outer surface of the housing, wherein the heat dissipation fins comprise: a plurality of first heat dissipation fins disposed to be spaced apart from each other; and a plurality of second heat dissipation fins disposed to be spaced apart from each other and disposed between the plurality of first heat dissipation fins that are adjacent to each other, and wherein on the basis of a first direction, the lengths of the first heat dissipation fins are longer than the lengths of the second heat dissipation fins.
    Type: Application
    Filed: November 16, 2022
    Publication date: October 17, 2024
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Jae Hoo JUNG, Ji Hyeon BAIK, Yong Bin LEE
  • Patent number: 7592708
    Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: September 22, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung-Gu Kim, Je-Gwang Yoo, Yong-Bin Lee, Yoo-Keum Wee, Seok-Hwan Huh, Chang-Sup Ryu
  • Publication number: 20090133902
    Abstract: A printed circuit board is disclosed. The printed circuit board, which may include an insulation layer, a first metal pad formed on the insulation layer, a second metal pad electrically coupled with the first metal pad and having an ionization tendency lower than that of the first metal pad, and a sacrificial electrode electrically coupled with the second metal pad to prevent corrosion in the first metal pad, can be utilized to prevent excessive etching that may otherwise occur due to galvanic corrosion between metal pads of different ionization tendencies.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 28, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chin-Kwan Kim, Tae-Gon Lee, Young-Mi Lee, Yoon-Hee Kim, Hwa-Jun Jung, Kui-Won Kang, Yong-Bin Lee
  • Publication number: 20090097220
    Abstract: A printed circuit board is disclosed. The printed circuit board, which has at least one pad on which a solder ball is to be placed, includes a solder resist that covers a surface of the printed circuit board, an opening part that exposes the pad and supports the solder ball, and an extended portion formed in a perimeter of the opening part that allows an underfill to flow in between the printed circuit board and the solder ball. With this printed circuit board, the underfill can be filled in more readily between the printed circuit board and the solder balls, when mounting a component on the printed circuit board.
    Type: Application
    Filed: January 29, 2008
    Publication date: April 16, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young-Mi Lee, Suk-Chang Hong, Yong-Bin Lee, Chin-Kwan Kim
  • Publication number: 20070298546
    Abstract: A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with the first circuit pattern is formed on the other surface, and a dielectric layer is selectively coated on the one surface such that the bump pad is exposed. The method includes layering a conductive layer on the other surface of the core board, coating a plating resist on the conductive layer, forming the bump by supplying electricity to the conductive layer to electroplate the bump pad, and removing the plating resist and the conductive layer.
    Type: Application
    Filed: April 13, 2007
    Publication date: December 27, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong-Jin Lee, Sun-Moon Kim, Mi-Seon Shin, Yong-Bin Lee
  • Publication number: 20070170586
    Abstract: Disclosed are a printed circuit board for a semiconductor package and a method of manufacturing the same. Specifically, a printed circuit board for a semiconductor package includes predetermined circuit patterns, having a wire bonding portion and a bump portion for mounting a semiconductor and a soldering portion for connection to external parts, in which the bump portion has a pre-solder formed using a tin or tin alloy electroplating process. According to this invention, the pre-solder, which is formed by reflow using an electroplating process, permits easy increase of the height thereof to thus enhance bondability and underfilling capability, may be formed to a desired thickness by controlling a plating thickness, and furthermore, may be applied to a fine pitch through a masking process.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 26, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventors: Yong Bin Lee, Kyoung Won Bae, Jong Min Choi, Eui Youn Yoo
  • Publication number: 20070080469
    Abstract: With a semiconductor package according to an aspect of the present invention comprising a board having circuit lines, solder resist formed on a surface of the board, and a chip mounted on the board and having at least one bump attached to at least a portion of the circuit lines, where the solder resist comprises a perimeter groove, which exposes at least a portion of the circuit lines, and an extension groove, which is connected to the perimeter groove, and where encapsulant is filled in the perimeter groove and the extension groove, the filling characteristics of the encapsulant is improved for greater reliability in the electrical connections between the chip and the board.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 12, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung-Gu Kim, Je-Gwang Yoo, Yong-Bin Lee, Yoo-Keum Wee, Seok-Hwan Huh, Chang-Sup Ryu