Abstract: A method of monitoring and managing performance of an artificial neural network model for an air interface may comprise: receiving, by a network (NW) including a communication node performing a function of monitoring and managing performance of an artificial neural network model, a performance metric of the artificial neural network model from a user equipment (UE); and controlling, by the communication node, activation or deactivation of the artificial neural network model according to the performance metric, wherein the artificial neural network model is activated to improve a main performance metric of a mobile communication system including the communication node and the UE connected through an air interface.

Abstract: A method of a terminal may comprise: receiving a first message including state information of a base station from the base station; identifying preliminary inactive state information included in the first message when the state information of the base station indicates a preliminary inactive state; and performing a cell selection based on the preliminary inactive state information.

Abstract: A method of a terminal may comprise: receiving a reference signal from a base station; generating channel information based on the reference signal; generating wavelet-transformed channel information by applying wavelet transform to the channel information; generating compressed channel information by compressing the wavelet-transformed channel information; and transmitting the compressed channel information to the base station.

Abstract: An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.

Abstract: A circuit for generating an internal voltage to be supplied to memory elements of a semiconductor memory chip during normal operation and for providing an external voltage to the memory elements during a burn-in test operation. The circuit may be constructed with a driver circuit (50) which receives an external voltage and is controlled to generate the internal voltage. A comparator (300) compares the internal voltage to a first reference voltage to produce a control signal G2 to control the driver circuit (50). An external voltage detector (100) compares a second reference voltage to the external voltage to generate control signal B2. A driver control circuit (200) is enabled by control signal B2, if the external voltage is less than the second reference voltage, to pass control signal G2 to the driver circuit and thereby enable generation of the internal voltage to be equal to, or less than, the operating voltage of the semiconductor memory chip.

Abstract: A data output buffer suitable for use in a semiconductor memory device includes a first input circuit coupled to a first data signal and a first control signal, e.g., an output enable signal, and a second input circuit coupled to a second data signal which is the inverse of the first data signal and the first control signal. The data output buffer also includes a pull-up circuit responsive to the output of the first input circuit for selectively raising the data output node to a high voltage level, e.g., Vcc, and a pull-down circuit responsive to the output of the second input circuit for selectively lowering the data output node to a low voltage level, e.g., Vss. The data output buffer further includes a preset circuit comprised of a first preset control circuit responsive to the output of the first input circuit and a second control signal, e.g., an inverse output enable signal, for selectively raising the data output node from the low voltage level to an intermediate voltage level, e.g.

Abstract: A write driver of a semiconductor memory device is disclosed which includes: a data input incorporating a noninverted data input portion and an inverted data input portion for buffering an inputted data signal and an inverted data signal in response to write enable signal; a pulse generator generating a first control pulse signal in response to a state transition of the data signal or inverted data signal and a phase-inverted second control pulse signal of the first control pulse signal in response to an inverted write enable signal; a transmitter for transmitting the inverted and noninverted data which have been buffered to a pair of data lines in response to the first control pulse signal; and a precharger for precharging the pair of data lines in response to the second control pulse signal.

Abstract: For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three

Abstract: A level converter for converting a TTL level of an input signal to a CMOS level comprises a NOR gate circuit (1), including a first voltage pull-up PMOS transistor (PI2), to which the TTL signal is inputted, an inverter (INV) connected to the NOR gate circuit, and a speed control circuit (2). The speed control circuit includes a second voltage pull-up PMOS transistor (PI4), and means are provided for connecting the first and second transistors in parallel between VCC and the input to the inverter. A fast conversion speed is obtained by turning on both PMOS transistors (PI2, PI4) when the TTL signal goes from the high level to the low level.

Abstract: An input translating circuit for a CMOS device is disclosed which can be operated without being influenced by a level of the supply voltage. This is made possible by providing a supply voltage level discriminating means consisting of a voltage dividing network for dividing the supply voltage into predetermined voltages and a level comparing means for comparing the divided voltage with the reference voltage level, and further by providing a constant voltage supply means, so that a trip voltage, used in the operation of the circuit, can be maintained at a constant level regardless of the variations of the supply voltage. Further, the circuit according to the present invention eliminates corresponding mask work requirements for the option of the power voltage in the manufacturing process, thereby lowering production complexity costs.

Abstract: A CMOS input buffer for converting the TTL level signals to the CMOS level signals, thereby being capable of stably operating within all allowable range of the power supply voltage, is disclosed. Said CMOS input buffer includes an inverter, a reference voltage generating circuit, a power supply voltage tracer circuit and an input circuit. The input circuit includes P-channel MOS transistors and N-channel MOS transistors so as to supply a stable logic output in response to the input signal of TTL level, regardless of variation of the power supply voltage Vcc, under the control of a voltage that is approximately proportional to the difference between the reference voltage and the power supply voltage within a fixed range of the power supply voltage.