Abstract: A multiplexer circuit in which high speed operation and high integration can be achieved by distributing the parasitic capacitance generated in the common output stage of pass transistor. A multiplexer circuit which outputs any one of input signals of 1 to n, input to the n pass transistors after selecting it at the common output stage, in response to the the selection signal of 1 to n (n=a natural number), comprising; input means receiving 1 to i input signals (1<i<n); a first switching means which select any one of the input signals in response to the 1 to i selection signals and output it to a first common output stage; a second switching means which select any one of the i+1 to n input signals in response to the i+1 to n selection signals and output it to a second common output stage; and an output means which has input stage connected to the first common output stage and output stage connected to the second common output stage and outputs the final output signal to the external circuit.