Patents by Inventor Yong-Chai Kwon
Yong-Chai Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11489184Abstract: An electrolyte including a mixture of hydroxynaphtoquinone and a precursor material thereof is provided. The electrolyte may achieve higher capacities.Type: GrantFiled: March 26, 2021Date of Patent: November 1, 2022Assignee: Foundation for Research and Business, Seoul National University of Science and TechnologyInventors: Yong Chai Kwon, Won Mi Lee, Gyun Ho Park
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Publication number: 20210305610Abstract: An electrolyte including a mixture of hydroxynaphtoquinone and a precursor material thereof is provided. The electrolyte may achieve higher capacities.Type: ApplicationFiled: March 26, 2021Publication date: September 30, 2021Applicant: Foundation for Research and Business, Seoul National University of Science and TechnologyInventors: Yong Chai KWON, Won Mi LEE, Gyun Ho PARK
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Patent number: 8367472Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.Type: GrantFiled: March 23, 2011Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Ho Lee, Dong Ho Lee, Eun Chul Ahn, Yong Chai Kwon
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Patent number: 8053807Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.Type: GrantFiled: September 28, 2010Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Publication number: 20110171781Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho LEE, Dong Ho LEE, Eun Chul AHN, Yong Chai KWON
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Patent number: 7939947Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.Type: GrantFiled: April 28, 2010Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Patent number: 7915710Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.Type: GrantFiled: July 31, 2008Date of Patent: March 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Ho Lee, Dong Ho Lee, Eun Chul Ahn, Yong Chai Kwon
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Patent number: 7884875Abstract: Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.Type: GrantFiled: October 3, 2007Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Publication number: 20110014748Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Patent number: 7825468Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.Type: GrantFiled: December 28, 2007Date of Patent: November 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Publication number: 20100207278Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.Type: ApplicationFiled: April 28, 2010Publication date: August 19, 2010Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Patent number: 7777323Abstract: Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.Type: GrantFiled: May 18, 2007Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Chai Kwon, Keum-Hee Ma, Kang-Wook Lee, Dong-Ho Lee, Seong-il Han
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Patent number: 7777345Abstract: A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.Type: GrantFiled: June 4, 2008Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jin Lee, Nam-Seog Kim, Yong-Chai Kwon, Hyun-Soo Chung, In-Young Lee, Son-Kwan Hwang
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Patent number: 7732328Abstract: A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.Type: GrantFiled: October 3, 2007Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee
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Patent number: 7602047Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.Type: GrantFiled: November 6, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee, In-Young Lee
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Patent number: 7588964Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.Type: GrantFiled: April 24, 2007Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Dong-Ho Lee, Myung-Kee Chung, Kang-Wook Lee, Sun-Won Kang, Keum-Hee Ma
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Publication number: 20090186446Abstract: Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the capping layer. The capping layer is coupled to the substrate by a bonding layer formed on the substrate, and the capping layer covers the semiconductor chip provided on the substrate. The processing of the substrate and the capping layer can be separately performed, thus allowing the material for the capping layer and/or the substrate to be selected to reduce (e.g., to minimize) a difference between the thermal expansion coefficients of the capping layer material and the substrate material.Type: ApplicationFiled: November 26, 2008Publication date: July 23, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Nam-Seog Kim, Keum-Hee Ma, Ho-Jin Lee
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Patent number: 7534656Abstract: An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.Type: GrantFiled: July 23, 2007Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., LtdInventors: Yong-Chai Kwon, Kang-Wook Lee, Gu-Sung Kim, Seong-Il Han, Keum-Hee Ma, Suk-Chae Kang, Dong-Hyeon Jang
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Publication number: 20090121323Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including an active surface and an inactive surface which faces the active surface, a device isolation layer and a pad stacked on the active surface; and a through electrode disposed in a first via hole and a second via hole and including a protruding part that protrudes from the pad, the first via hole penetrating the semiconductor substrate, the second via hole penetrating the device insulation layer and the pad continuously, wherein at least a surface of the protruding part of the through electrode is formed of an oxidation resistance-conductive material.Type: ApplicationFiled: November 7, 2008Publication date: May 14, 2009Applicant: Samsung Electronics Co., LtdInventors: Yong-Chai KWON, Nam-Seong KIM
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Patent number: 7521657Abstract: An assembly may include a wafer and a plate may be mounted on the wafer. The wafer may have image sensor chips and scribe lines demarcating each image sensor chip. The image sensor chip may include an active surface. Chip pads and a micro-lens may be provided on the active surface. A photo-sensitive adhesive pattern may be provided between the plate and a region of the active surface between the chip pads and the micro-lens. An image sensor device implementing an image sensor chip having an individual plate may also be provided.Type: GrantFiled: June 10, 2005Date of Patent: April 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Chai Kwon, Kang-Wook Lee, Gu-Sung Kim, Keum-Hee Ma, Seong-Il Han