Abstract: A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction.

Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.

Abstract: A semiconductor memory device includes first and second active pillar structures protruding at an upper part of a substrate, buried bit lines each extending in a first direction, and first gate patterns and second gate patterns each extending in a second direction. The first and second active pillar structures occupy odd-numbered and even-numbered rows, respectively. The first and the second active pillar structures also occupy even-numbered and odd-numbered columns, respectively. The columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures. Each buried bit line is connected to lower portions of the first active pillar structures which occupy one of the even-numbered columns and to lower portions of the second active pillar structures which occupy an adjacent one of the odd-numbered columns.

Abstract: A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.

Abstract: A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.

Abstract: A semiconductor device includes a substrate having a first area and a second area, a first active structure disposed in the first area, a second active structure disposed in the second area, a first transistor disposed in the first area and a second transistor disposed in the second area. The second active structure may have a height substantially the same as a height of the first active structure. The first transistor includes a first gate structure enclosing an upper portion of the first active structure, a first impurity region formed at a lower portion of the first active structure, and a second impurity region formed at the upper portion of the first active structure. The second transistor includes a second gate structure formed on the second active structure and third impurity regions formed at an upper portion of the second active structure.

Abstract: A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween.

Abstract: A semiconductor device includes an insulation layer disposed on a substrate having a first area and a second area, a first wiring disposed on the insulation layer in the first area, a first active structure disposed on the first wiring, a first gate insulation layer enclosing the first upper portion, a first gate electrode disposed on the first gate insulation layer, a first impurity region disposed at the first lower portion, and a second impurity region disposed at the first upper portion. The first wiring may extend in a first direction. The first active structure includes a first lower portion extending in the first direction and a first upper portion protruding from the first lower portion. The first gate electrode may extend in a second direction. The first impurity region may be electrically connected to the first wiring.

Abstract: An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract: An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.

Abstract: Provided is a capacitor-less DRAM device including: an insulating layer formed on a semiconductor substrate; a silicon layer formed on the insulating layer, wherein a trench is formed inside the silicon layer; and an offset spacer formed on both sidewalls of the trench and protruded upward through the silicon layer. A gate insulating layer is formed on a bottom of the trench, and a gate electrode is formed to be buried in the gate insulating layer and in the trench and the offset spacer. A source region and a drain region are formed in the silicon layer on both sides of the offset spacer so as not to overlap with the gate electrode. A channel region is formed in the silicon layer below the gate insulating layer to be self-aligned with the gate electrode.

Abstract: A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern.

Abstract: A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract: In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.

Abstract: An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.

Abstract: In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.

Abstract: A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure.