Abstract: A stick type cosmetic container capable of depleting a remaining amount of cosmetics is described. The cosmetic holder has raising and lowering ribs coupled to raising and lowering guide grooves of a protection tubular body, allowing cosmetics to appear and disappear in a proper length. One or more engaging ribs are formed in a stepped shape in the cosmetic holder. A stopper is provided on opposite portions of a flat second side outer circumferential surface of the raising and lowering supporting part and configured to be mutually caught by a lower end of the engagement rib to limit the upward movement of the cosmetics. The cosmetic holder is separably engaged to a tubular body through one or more engagement ribs. The tubular body is configured to be raised independently secondarily while being released from an engagement force from the engagement rib of the cosmetic holder.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: A risk determining method and apparatus are disclosed. The risk determining method includes obtaining a plurality of sets of elevation-velocity data, determining a diffusion prediction coefficient based on the obtained sets of elevation-velocity data, determining at least one of a volatilization factor (VF) or a particulate emission factor (PEF) based on the determined diffusion prediction coefficient, and determining a risk from an inhalation exposure based on the at least one of the VF or the PEF.

Abstract: The present invention relates to novel mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, a novel crystalline form thereof, and a process for preparing the same. More specifically, the present invention relates to mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, which is excellent in stability, solubility, and bioavailability when it is administered not only alone but also in combination with other drugs and which has a high purity, a crystalline form thereof, and a process for preparing the same.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: Methods of treating a subject with diabetes or pre-diabetes include administering an effective amount of a phenyl propionic acid of the Formula (I), an isomer, or a pharmaceutically acceptable salt thereof to the subject to lower one or more of HbA1c level, fasting plasma glucose level, 2-hour oral glucose tolerance test (OGTT) result level, and random plasma glucose level.

Abstract: The present invention relates to a use of imidazopyrimidine or imidazotriazine compounds of Chemical Formula 1, or pharmaceutically acceptable salts, solvates, or hydrates thereof, for preventing, alleviating or treating cognitive disorder or for improving enhancing cognitive function.

Abstract: The present invention relates to novel mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yppyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, a novel crystalline form thereof, and a process for preparing the same. More specifically, the present invention relates to mesylate salt of N-(5-(4-(4-((dimethylamino)methyl)-3-phenyl-1H-pyrazol-1-yl)pyrimidine-2-ylamino)-4-methoxy-2-morpholinophenyl)acrylamide, which is excellent in stability, solubility, and bioavailability when it is administered not only alone but also in combination with other drugs and which has a high purity, a crystalline form thereof, and a process for preparing the same.

Abstract: A scan driver includes a first transistor including gate, first, and second electrodes coupled to a Q node, a scan clock line, and a scan line. A second transistor includes gate and first electrodes coupled to a scan carry line, and a second electrode coupled to the Q node. A third transistor includes gate and first electrodes coupled to a first control line and a sensing carry line. A fourth transistor includes a gate and first electrode coupled to the sensing carry line and the third transistor first electrode. A fifth transistor includes gate, first, and second electrodes coupled to a fourth transistor second electrode, a second control line, and a node. A capacitor includes first and second electrodes coupled to the fifth transistor first and gate electrodes. A sixth transistor includes gate, first, and second electrodes coupled to a third control line, the node, and the Q node.

Abstract: Disclosed herein are compositions for fixing tissue for cytologic, histomorphologic, and/or molecular analysis (e.g., DNA, RNA, and/or protein analysis). In some embodiments, the fixatives are aldehyde-free fixatives, for example, formaldehyde- or formalin-free fixatives. Particular disclosed compositions include buffered ethanol. The buffer is a phosphate buffer or phosphate buffered saline (PBS) in some examples. In further embodiments, the fixative includes additional components, such as glycerol and/or acetic acid.

Abstract: A light emitting display device including: a first pixel including a first lower storage electrode, a first gate electrode of a first driving transistor, and a first upper storage electrode; and a second pixel provided near the first pixel, and including a second lower storage electrode, a second gate electrode of a second driving transistor, and a second upper storage electrode. In a plan view, the first gate electrode and the second gate electrode have first sides facing each other, the first side of the first gate electrode is positioned inside a border of the first lower storage electrode or the first upper storage electrode in a plan view, and the first side of the second gate electrode is positioned inside a border of the second lower storage electrode or the second upper storage electrode in a plan view.

Abstract: A light emitting display device including a first pixel including a first driving transistor, a first input transistor, a first initialization transistor, a first storage capacitor, and a first light emitting diode (LED); and a second pixel including a second driving transistor, a second input transistor, a second initialization transistor, a second storage capacitor, and a second light emitting diode (LED. The first pixel further includes a first gate electrode connecting member connecting a first gate electrode of the first driving transistor and the first input transistor; the second pixel further includes a second gate electrode connecting member connecting a second gate electrode of the second driving transistor and the second input transistor; the first light emitting diode (LED) includes a first anode; the second light emitting diode (LED) includes a second anode; and the first gate electrode connecting member does not overlap the second anode in a plan view.

Abstract: Proposed herein is a dispenser type beverage container including: a cartridge cover member having a cartridge insertion space into which a cartridge storing a target material to be mixed is inserted; a main body located below the cartridge cover member to contain the target material discharged from the cartridge in an inner space thereof; and a button member of which the inner face of the upper portion capable of doing a rectilinear motion is arranged to meet an end of the cartridge inserted into the cartridge cover member, so that the target material stored in the cartridge is discharged into the main body when the upper portion is pressed down by external pressure.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A scan driver includes a first transistor including gate, first, and second electrodes coupled to a Q node, a scan clock line, and a scan line. A second transistor includes gate and first electrodes coupled to a scan carry line, and a second electrode coupled to the Q node. A third transistor includes gate and first electrodes coupled to a first control line and a sensing carry line. A fourth transistor includes a gate and first electrode coupled to the sensing carry line and the third transistor first electrode. A fifth transistor includes gate, first, and second electrodes coupled to a fourth transistor second electrode, a second control line, and a node. A capacitor includes first and second electrodes coupled to the fifth transistor first and gate electrodes. A sixth transistor includes gate, first, and second electrodes coupled to a third control line, the node, and the Q node.

Abstract: A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.