Patents by Inventor Yong-Cyuan Chen

Yong-Cyuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289187
    Abstract: The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods.
    Type: Grant
    Filed: December 25, 2023
    Date of Patent: April 29, 2025
    Assignee: PowerX Semiconductor Corporation
    Inventors: Yong Cyuan Chen, Jui Teng Chan, Chung-Kang Wu
  • Publication number: 20250132672
    Abstract: The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.
    Type: Application
    Filed: January 16, 2024
    Publication date: April 24, 2025
    Inventors: Jui Teng CHAN, Yong Cyuan CHEN, Chung-Kang WU
  • Publication number: 20250132671
    Abstract: The present disclosure provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit includes a primary side circuit, an isolation circuit and a secondary side circuit. The primary side circuit generates a primary side signal according to a first input signal and a second input signal. The isolation circuit converts the primary side signal into a secondary side signal. The secondary side circuit receives the secondary side signal through the isolation circuit, to generate an output signal. The signal delay setting circuit is coupled to the secondary side circuit, calculates a delay time according to a voltage difference between an alternative terminal and a secondary side ground terminal of the isolation integrated circuit, and delays the secondary side signal according to the delay time, to control the duty ratio of the output signal.
    Type: Application
    Filed: January 15, 2024
    Publication date: April 24, 2025
    Inventors: Jui Teng CHAN, Yong Cyuan CHEN, Jo-Yu WANG, Chih-Yuan HSU, Chung-Kang WU
  • Publication number: 20250062940
    Abstract: The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods.
    Type: Application
    Filed: December 25, 2023
    Publication date: February 20, 2025
    Inventors: Yong Cyuan CHEN, Jui Teng CHAN, Chung-Kang WU
  • Publication number: 20220321012
    Abstract: A switching regulator includes a first switch, a second switch, an inductor coupled to the first and second switches, and a control circuit. The control circuit controls the first switch to be ON for an ON time period. Next, the control circuit controls the first and second switches to be OFF for a first dead time period. Next, the control circuit controls the second switch to be ON for a synchronous rectification time period. Next, the control circuit controls the first and second switches to be OFF for a second dead time period. Next, the control circuit controls the second switch to be ON for a zero-voltage-switching pulse time period. Next, the control circuit controls the first and second switches to be OFF for a third dead time period. By the above operations, the first switch achieves soft switching.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Inventors: Yong-Cyuan Chen, Tzu-Chen Lin, Yi-Wei Lee, Ta-Yung Yang