Patents by Inventor Yong-Da Chiu

Yong-Da Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTROLESS SEMICONDUCTOR BONDING STRUCTURE, ELECTROLESS PLATING SYSTEM AND ELECTROLESS PLATING METHOD OF THE SAME
    Publication number: 20220056589
    Abstract: An electroless semiconductor bonding structure, an electroless plating system and an electroless plating method of the same are provided. The electroless semiconductor bonding structure includes a first substrate and a second substrate. The first substrate includes a first metal bonding structure disposed adjacent to a first surface of the first substrate. The second substrate includes a second metal bonding structure disposed adjacent to a second surface of the second substrate. The first metal bonding structure connects to the second metal bonding structure at an interface by electroless bonding and the interface is substantially void free.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Wei CHIANG, Shin-Luh TARNG, Chih-Pin HUNG, Shiu-Chih WANG, Yong-Da CHIU
  • Semiconductor packages
    Patent number: 10872861
    Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC. KAOHSIUNG, TAIWAN
    Inventors: Yong-Da Chiu, Shiu-Chih Wang, Shang-Kun Huang, Ying-Ta Chiu, Shin-Luh Tarng, Chih-Pin Hung
  • SEMICONDUCTOR PACKAGES
    Publication number: 20190244909
    Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yong-Da CHIU, Shiu-Chih WANG, Shang-Kun HUANG, Ying-Ta CHIU, Shin-Luh TARNG, Chih-Pin HUNG
  • Semiconductor device and method for manufacturing the same
    Patent number: 10096569
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 9, 2018
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., NATIONAL CHUNG HSING UNIVERSITY
    Inventors: Ying-Ta Chiu, Shang-Kun Huang, Yong-Da Chiu, Jenn-Ming Song
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20180247913
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.
    Type: Application
    Filed: February 27, 2017
    Publication date: August 30, 2018
    Applicants: ADVANCED SEMICONDUCTOR ENGINEERING, INC., NATIONAL CHUNG HSING UNIVERSITY
    Inventors: Ying-Ta CHIU, Shang-Kun HUANG, Yong-Da CHIU, Jenn-Ming SONG
  • Semiconductor packages
    Patent number: 9917071
    Abstract: A semiconductor package includes: a first substrate including a first interconnection structure extending from a surface of the first substrate, the first interconnection structure including grains of a first size, a second substrate including: a second interconnection structure comprising grains of a second size, and a third interconnection structure disposed between the first interconnection structure and the second interconnection structure, the third interconnection structure including grains of a third size, a first sidewall inclined at a first angle to a reference plane and a second sidewall inclined at a second angle to the reference plane, wherein the first angle is different from the second angle, the first sidewall is disposed between the first substrate and the second sidewall, and the third size is smaller than both the first size and the second size.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 13, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Ta Chiu, Yong-Da Chiu, Dao-Long Chen, Chih-Cheng Lee, Chih-Pin Hung