Abstract: A semiconductor device includes a substrate of a first conductivity type, a gate electrode on the substrate, a first high concentration impurity region of the first conductivity type that is disposed on a first side of the gate electrode, a first well of the first conductivity type that is disposed under the first high concentration impurity region and surrounds the first high concentration impurity region, a second well of a second conductivity type that overlaps with a portion of the gate electrode and is adjacent to the first well, and a first deep well of the second conductivity type that is disposed under the first well and the second well, the first deep well and the first high concentration impurity region being responsive to a first voltage.

Abstract: A schottky diode includes a conduction layer of a first conduction type, a well region of a second conduction type disposed in the conduction layer, a first isolation region disposed in the conduction layer, where the first isolation region is spaced apart from the well region, a first junction region of the second conduction type disposed in the conduction layer, where the first junction region is adjacent the first isolation region and spaced apart from the well region, a second junction region of the first conduction type disposed in the conduction layer, where the second junction region is adjacent the first isolation region and a schottky electrode covering a schottky junction surface corresponding to an upper surface of the conduction layer between the well region and the first junction region.

Abstract: The electronic device having a Schottky diode includes first and second electrodes disposed on a semiconductor substrate and spaced apart from each other. A first semiconductor region is formed within the semiconductor substrate. The first semiconductor region may include a first surface portion in contact with the second electrode, forming a Schottky diode with the second electrode. A second semiconductor region having the same conductivity-type as the first semiconductor region and overlapping the first electrode is formed within the semiconductor substrate. A third semiconductor region having a different conductivity-type from the first semiconductor region, and having a first portion and a second portion spaced apart from each other, is formed within the semiconductor substrate. An isolation region is disposed between the second and the third semiconductor regions. The isolation region includes a first isolation portion and a second isolation portion spaced apart from each other.

Abstract: A semiconductor device includes a substrate of a first conductivity type, a gate electrode on the substrate, a first high concentration impurity region of the first conductivity type that is disposed on a first side of the gate electrode, a first well of the first conductivity type that is disposed under the first high concentration impurity region and surrounds the first high concentration impurity region, a second well of a second conductivity type that overlaps with a portion of the gate electrode and is adjacent to the first well, and a first deep well of the second conductivity type that is disposed under the first well and the second well, the first deep well and the first high concentration impurity region being responsive to a first voltage.

Abstract: The electronic device having a Schottky diode includes first and second electrodes disposed on a semiconductor substrate and spaced apart from each other. A first semiconductor region is formed within the semiconductor substrate. The first semiconductor region may include a first surface portion in contact with the second electrode, forming a Schottky diode with the second electrode. A second semiconductor region having the same conductivity-type as the first semiconductor region and overlapping the first electrode is formed within the semiconductor substrate. A third semiconductor region having a different conductivity-type from the first semiconductor region, and having a first portion and a second portion spaced apart from each other, is formed within the semiconductor substrate. An isolation region is disposed between the second and the third semiconductor regions. The isolation region includes a first isolation portion and a second isolation portion spaced apart from each other.

Abstract: A semiconductor device includes at least one gate electrode on a substrate structure, at least one drain region doped with impurities of a first conductivity type, a first well region doped with impurities of the first conductivity type under the at least one drain region, and at least one source region doped with impurities of the first conductivity type. The device also includes a first barrier impurity region and a second barrier impurity region. The first barrier impurity region is doped with impurities of the first conductivity type and electrically insulating upper and lower portions of the substrate structure from each other. The second barrier impurity region is doped with impurities of a second conductivity type. A portion of the second barrier impurity region has an uneven shape and overlaps the at least one drain region.

Abstract: A semiconductor device is provided that includes a substrate including a device region and a peripheral region surrounding the device region, a first interconnection including one or more first conductive lines extending in a first direction, a second interconnection including one or more second conductive lines extending in the first direction, the second interconnection spaced apart from the first interconnection, a first conductive plate and a second conductive plate spaced apart from each other, the first conductive plate corresponding to the first interconnection and the second conductive plate corresponding to the second interconnection, one or more first vias connecting the first conductive lines to the first conductive plate and overlapping the device region and one or more second vias connecting the second conductive lines to the second conductive plate, the second vias overlapping the device region and arranged in a staggered, alternating configuration with the one or more first vias.

Abstract: A semiconductor device includes at least one gate electrode on a substrate structure, at least one drain region doped with impurities of a first conductivity type, a first well region doped with impurities of the first conductivity type under the at least one drain region, and at least one source region doped with impurities of the first conductivity type. The device also includes a first barrier impurity region and a second barrier impurity region. The first barrier impurity region is doped with impurities of the first conductivity type and electrically insulating upper and lower portions of the substrate structure from each other. The second barrier impurity region is doped with impurities of a second conductivity type. A portion of the second barrier impurity region has an uneven shape and overlaps the at least one drain region.

Abstract: A semiconductor device is provided that includes a substrate including a device region and a peripheral region surrounding the device region, a first interconnection including one or more first conductive lines extending in a first direction, a second interconnection including one or more second conductive lines extending in the first direction, the second interconnection spaced apart from the first interconnection, a first conductive plate and a second conductive plate spaced apart from each other, the first conductive plate corresponding to the first interconnection and the second conductive plate corresponding to the second interconnection, one or more first vias connecting the first conductive lines to the first conductive plate and overlapping the device region and one or more second vias connecting the second conductive lines to the second conductive plate, the second vias overlapping the device region and arranged in a staggered, alternating configuration with the one or more first vias.

Abstract: A semiconductor integrated circuit device and method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate including a first conductivity type impurity such that the first conductivity type substrate has a first impurity concentration; forming a buried impurity layer using blank implant such that the buried impurity layer includes a first conductivity type impurity and has a second impurity concentration higher than the first impurity concentration; forming an epitaxial layer on the substrate having the buried impurity layer thereon; and forming semiconductor devices and a device isolation region in or on the epitaxial layer.

Abstract: Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The method includes: forming a mask film, which exposes a portion of a substrate, on the substrate; forming a first buried impurity layer, which contains impurities of a first conductivity type and of a first concentration, in a surface of the exposed portion of the substrate by using the mask film; removing the mask film; forming a second buried impurity layer, which contains impurities of a second conductivity type and of a second concentration, using blank implantation; and forming an epitaxial layer on the substrate having the first and second buried impurity layers, wherein the first concentration is higher than the second concentration.

Abstract: A semiconductor integrated circuit device and method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate including a first conductivity type impurity such that the first conductivity type substrate has a first impurity concentration; forming a buried impurity layer using blank implant such that the buried impurity layer includes a first conductivity type impurity and has a second impurity concentration higher than the first impurity concentration; forming an epitaxial layer on the substrate having the buried impurity layer thereon; and forming semiconductor devices and a device isolation region in or on the epitaxial layer.

Abstract: Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The method includes: forming a mask film, which exposes a portion of a substrate, on the substrate; forming a first buried impurity layer, which contains impurities of a first conductivity type and of a first concentration, in a surface of the exposed portion of the substrate by using the mask film; removing the mask film; forming a second buried impurity layer, which contains impurities of a second conductivity type and of a second concentration, using blank implantation; and forming an epitaxial layer on the substrate having the first and second buried impurity layers, wherein the first concentration is higher than the second concentration.

Abstract: A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.

Abstract: A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.

Abstract: An address driver includes an energy recovery circuit and an output stage connected to the energy recovery circuit. The output stage is connected to the energy recovery circuit and is formed of a pull-up MOS transistor and a pull-down MOS transistor in series. A source terminal of the pull-up MOS transistor is connected to the energy recovery circuit, and a bulk terminal of the pull-up MOS transistor is connected to a node providing a reverse bias between the source terminal and the bulk terminal of the pull-up MOS transistor. A display device employing the address driver is also provided.

Abstract: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

Abstract: High voltage schottky diodes are provided including a first conductivity type semiconductor substrate and a second conductivity type well region defined by the substrate. A first conductive film is provided on a surface of the substrate including the well. A conductive electrode is provided on at least one side of the first conductive film above the substrate including the well. An insulating film is provided between the conductive electrode and the substrate. A cathode contact region is provided outside the conductive electrode remote from the first conductive film. The cathode contact region is doped with high concentration impurities having a second conductive type.

Abstract: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

Abstract: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.