Abstract: In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract: An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Abstract: An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described. The data transmission circuit includes a pair of transmission gates for transferring the true and complement data signals in a write cycle, a pair of inverting stages connected between respective ones of the transmission gates and true and complement input/output (I/O) bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalizing stage for precharging and equalizing true and complement I/O bus lines in a precharge cycle.