Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract: An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Abstract: A structure for protecting the reading area of a compact disc includes a transparent protective film and a two-side-adhesive ring. The protective film has an outer diameter equal to or slightly smaller than the outer diameter of the compact disc, and a center hole with a diameter greater than the protruded ring of the compact disc. The two-side-adhesive ring has an inner diameter equal to or slightly greater than the protruded ring of the compact disc, and an outer diameter greater than the inner diameter thereof by 2-5 mm. The structure is applied by an applicator to the compact disc such that the protective film is attached to the reading area of the compact disc by static attraction, and further that the inner annular portion of the protective film is held by the two-side-adhesive ring adhering to the annular portion surrounding the protruded ring of the compact disc.

Abstract: A convertible roller footwear comprises: a sole; an elongate bushing embedded in the sole and extending in a transverse direction of the sole to terminate at opposite open ends, the bushing having an inner circumferential surface and generally hemispherical recesses disposed on the inner circumferential surface in the vicinity of the opposite ends of the bushing; a plurality of roller assemblies, each including a hollow nipple removably fitted into the bushing, the nipple having a radial through-hole formed adjacent to an internal end of the nipple to receive a ball therein, a pushpin slidably inserted through the nipple, the pushpin having an annular groove for selective communication with the radial through-hole, the pushpin movable between a pushed-in position for allowing the ball to move radially inwardly into engagement with the annular groove and a pulled-out position for causing the ball to move radially outwardly into engagement with the recesses, and a roller rotatably mounted on an external end of

Abstract: An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described. The data transmission circuit includes a pair of transmission gates for transferring the true and complement data signals in a write cycle, a pair of inverting stages connected between respective ones of the transmission gates and true and complement input/output (I/O) bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalizing stage for precharging and equalizing true and complement I/O bus lines in a precharge cycle.