Patents by Inventor Yong-En Syu
Yong-En Syu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11158534Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.Type: GrantFiled: May 7, 2019Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
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Patent number: 11063117Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.Type: GrantFiled: April 20, 2017Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung Cheng, Yong-En Syu, Kuo-Hwa Tzeng, Ke-Dian Wu, Cheng-Ta Wu, Yeur-Luen Tu, Ming-Che Yang, Wei-Kung Tsai
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Publication number: 20190259655Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
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Patent number: 10304723Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.Type: GrantFiled: February 26, 2018Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
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Publication number: 20190157138Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.Type: ApplicationFiled: February 26, 2018Publication date: May 23, 2019Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
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Patent number: 10283702Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.Type: GrantFiled: December 18, 2017Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
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Publication number: 20180308928Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung CHENG, Yong-En SYU, Kuo-Hwa TZENG, Ke-Dian WU, Cheng-Ta WU, Yeur-Luen TU, Ming-Che YANG, Wei-Kung TSAI
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Publication number: 20180108836Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.Type: ApplicationFiled: December 18, 2017Publication date: April 19, 2018Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
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Patent number: 9847478Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.Type: GrantFiled: March 9, 2012Date of Patent: December 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
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Patent number: 9711521Abstract: The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.Type: GrantFiled: August 31, 2015Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yong-En Syu, Kuan-Chi Tsai, Kuo-Yu Cheng, Keng-Yu Chen, Shih-Shiung Chen, Shao-Yu Chen, Wei-Kung Tsai, Yu-Lung Yeh
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Publication number: 20170062452Abstract: The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Yong-En Syu, Kuan-Chi Tsai, Kuo-Yu Cheng, Keng-Yu Chen, Shih-Shiung Chen, Shao-Yu Chen, Wei-Kung Tsai, Yu-Lung Yeh
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Patent number: 9269591Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.Type: GrantFiled: March 24, 2014Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alex Kalnitsky, Chung-Long Chang, Yung-Chih Tsai, Tsung-Yu Yang, Keng-Yu Chen, Yong-En Syu
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Patent number: 9159916Abstract: A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.Type: GrantFiled: November 30, 2012Date of Patent: October 13, 2015Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ting-Chang Chang, Min-Chen Chen, Yong-En Syu, Kuan-Chang Chang, Fu-Yen Jian
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Publication number: 20150270143Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.Type: ApplicationFiled: March 24, 2014Publication date: September 24, 2015Inventors: Alex Kalnitsky, Chung-Long Chang, Yung-Chih Tsai, Tsung-Yu Yang, Keng-Yu Chen, Yong-En Syu
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Publication number: 20140063903Abstract: A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.Type: ApplicationFiled: November 30, 2012Publication date: March 6, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ting-Chang CHANG, Min-Chen CHEN, Yong-En SYU, Kuan-Chang CHANG, Fu-Yen JIAN
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Publication number: 20130234094Abstract: Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
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Patent number: 8427879Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.Type: GrantFiled: December 22, 2009Date of Patent: April 23, 2013Assignee: Acer IncorporatedInventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu
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Publication number: 20130009124Abstract: A type of resistance random access memory structure having the function of diode rectification includes a first electrode, a second electrode and a resistance conversion layer. The resistance conversion layer is disposed between the first electrode and the second electrode; and it includes a first oxidized insulating layer which is adjacently connected to the first electrode; a second oxidized insulating layer which is adjacently connected to the second electrode; as well as an energy barrier turning layer disposing between the first oxidized insulating layer and the second oxidized insulating layer. An energy barrier high can be adjusted and controlled to change the resistance by voltage between the energy barrier turning layer and the first oxidized insulating layer. A fixed energy barrier is formed between the second oxidized insulating layer and the energy barrier turning layer, so that the resistance random access memory element features the function of diode rectification.Type: ApplicationFiled: September 20, 2011Publication date: January 10, 2013Inventors: Ting-Chang CHANG, Yong-En SYU, Fu-Yen JIAN, Ming-Jinn TSAI
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Publication number: 20110096610Abstract: There is a method for enabling a SONOS transistor to be used as both a switch and a memory. FN tunneling is carried out through the source or drain of the transistor, so as to further change the state of electrons stored in an upper charge storage layer adjacent to the drain or source, and the variation in gate-induced drain leakage is used to recognize the memory state of the drain and source. A stable threshold voltage of the transistor is always maintained during this operation. The present invention enables one single transistor having dual features of switch and memory, while being provided with a two-bit memory effect, thus providing a higher memory density in comparison with a general transistor.Type: ApplicationFiled: December 22, 2009Publication date: April 28, 2011Applicant: ACER INCORPORATEDInventors: Ting-Chang Chang, Shih-Ching Chen, Te-Chih Chen, Fu-Yen Jian, Yong-En Syu