Patents by Inventor Yong Eun

Yong Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060151839
    Abstract: Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.
    Type: Application
    Filed: November 8, 2005
    Publication date: July 13, 2006
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Young Kim, Jun Chang, Min Lee, Yong Eun
  • Publication number: 20050118814
    Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.
    Type: Application
    Filed: July 12, 2004
    Publication date: June 2, 2005
    Inventors: Hyung Kim, Sung Jung, Yong Eun
  • Publication number: 20050085059
    Abstract: The present invention relates to a method for forming a word line wherein a gate electrode comprises aluminum silicide (AlSix) having low electrical resistance and stress to form a word line having low specific resistance, thereby increasing processing speed of a device and repressing micro-crack and lifting effects by stress alleviation between films to prevent fail of a device.
    Type: Application
    Filed: June 30, 2004
    Publication date: April 21, 2005
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jae Kim, Su Kim, Yong Eun