Patents by Inventor Yong-Fang Chiang

Yong-Fang Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190080996
    Abstract: A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.
    Type: Application
    Filed: February 2, 2018
    Publication date: March 14, 2019
    Applicant: ChipMOS Technologies Inc.
    Inventors: Pi-Chang Chen, Yong-Fang Chiang
  • Patent number: 10211142
    Abstract: A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: February 19, 2019
    Assignee: ChipMOS Technologies Inc.
    Inventors: Pi-Chang Chen, Yong-Fang Chiang