Abstract: A TEM specimen kit is disclosed, which comprises: (a) a top substrate and a bottom substrate, the top and the bottom substrates being transparent and substantially parallel to each other; (b) a first spacer and a second spacer, located beneath the top substrate and sitting on the bottom substrate, the second spacer being opposite to and spaced apart from the first spacer at a distance of d; and (c) a chamber formed between the top and bottom substrate and between the first and second spacer, the chamber having two ends open to the atmosphere and characterized by having a height defined by the thickness h of the spacer, wherein the height being smaller than the diameter of a red blood cell. Also enclosed are methods for preparing a dry specimen for TEM nanoparticle characterization, and methods for analyzing TEM images of nanoparticles in a liquid sample.

Abstract: A TEM specimen kit is disclosed, which comprises: (a) a top substrate and a bottom substrate, the top and the bottom substrates being transparent and substantially parallel to each other; (b) a first spacer and a second spacer, located beneath the top substrate and sitting on the bottom substrate, the second spacer being opposite to and spaced apart from the first spacer at a distance of d; and (c) a chamber formed between the top and bottom substrate and between the first and second spacer, the chamber having two ends open to the atmosphere and characterized by having a height defined by the thickness h of the spacer, wherein the height being smaller than the diameter of a red blood cell. Also enclosed are methods for preparing a dry specimen for TEM nanoparticle characterization, and methods for analyzing TEM images of nanoparticles in a liquid sample.

Abstract: A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.

Abstract: The present invention provides an on-chip thin film phase plate for a releasing charging, comprising a chip substrate having one or more apertures; and a thin film layer attached to the top surface of the chip substrate. The present invention also provides a method for observing organic material by TEM, which uses the above-mentioned on-chip thin film phase plate in a TEM system.

Abstract: The present invention provides an on-chip thin film phase plate for a releasing charging, comprising a chip substrate having one or more apertures; and a thin film layer attached to the top surface of the chip substrate. The present invention also provides a method for observing organic material by TEM, which uses the above-mentioned on-chip thin film phase plate in a TEM system.

Abstract: A specimen kit having a tiny chamber is disclosed for a specimen preparation for TEM. The space height of the chamber is far smaller than dimensions of blood cells and therefore is adapted to sort nanoparticles from the blood cells. The specimen prepared under this invention is suitable for TEM observation over a true distribution status of nanoparticles in blood. The extremely tiny space height in Z direction eliminates the possibility of aggregation of the nanoparticles and/or agglomeration in Z direction during drying; therefore, a specimen prepared under this invention is suitable for TEM observation over the dispersion and/or agglomeration of nanoparticles in a blood.

Abstract: Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

Abstract: Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

Abstract: Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

Abstract: Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

Abstract: The present invention is a method of fabricating a dynamic random access memory. The node contact opening and the capacitor opening are combined in a step of the dual damascene opening process during the capacitor formation. The bottom of the capacitor is embedded in the dual damascene opening. The conducting layer used for forming the bottom plates is polished by chemical mechanical polishing to form the bottom plates that are separated each other. Therefore, patterning of bottom plate by photolithography and etching is not necessary in the present invention.

Abstract: A method of fabricating a dynamic random access memory is described. The surrounding of a capacitor is covered with stop layers to prevent damage during the etching process for forming a bit line contact opening. A first dielectric layer is formed and it is patterned to form a capacitor opening therein. A conformal first stop layer is formed and covers the first dielectric layer and the capacitor opening. A part of the conformal first stop layer on the first source/drain is removed to form a self-aligned node contact opening. The capacitor is formed in the capacitor opening and the self-aligned node contact opening. A conformal second stop layer layer are formed over the substrate. A part of the second dielectric layer over the second source/drain, the conformal second stop layer, the first stop layer and the first dielectric layer underneath is removed to form a self-aligned bit line contact opening. A bit line is formed over the third dielectric layer and within the self-aligned bit line contact opening.

Abstract: A method of fabricating a shallow trench isolation structure includes defining a shallow trench isolation region on a substrate covered by a first oxide layer and a mask layer. Then, covering the inner surface of the shallow trench with a silicon nitride layer. After a thermal treatment, two oxide layers are formed at the two sides of the silicon nitride layer, respectively. Then, another oxide layer is formed to fill the shallow trench. Next, a planarization process is performed until the mask layer is exposed. The mask layer and the first oxide layer and the oxide layer higher than the substrate are removed.

Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.

Abstract: A method of manufacturing a cobalt suicide layer in the present invention has a silicon layer formation step. The silicon layer is formed at the interface between the cobalt layer and titanium layer, therefore the interface is smoother in this invention than in other conventional methods, and there are no voids formed at the interface. Moreover, consumption of the silicon can be controlled by adjusting the thickness of the silicon layer.

Abstract: A method to determine a desired thickness for a surface layer through which ion implantation will take place in order to control the shape of the implantation profile to minimize the formation of flaws includes choosing a maximum angle .theta. between solid phase epitaxial regrowth fronts, determining a projected range of ion implantation distance Rp into the substrate and a projected standard deviation .DELTA.Rp along a first axis direction and a projected standard deviation .DELTA.Y along a second axis direction. These values are then substituted into the following equation to solve for thickness t of the surface layer: t=Rp+cos.theta.[[(.DELTA.Y sin .theta.).sup.2 +(.DELTA.Rp cos .theta.).sup.2 ].sup.0.5 ] After the layer is placed onto the substrate, the implantation step is carried out. Annealing is then performed to recrystallize the amorphous zone. The morphology of the surface being implanted through can also be modified in order to control the directions of recrystallization upon annealing.

Abstract: A field effect transistor which is not susceptible to mask edge detects at its gate spacer oxides. The transistor is formed upon a semiconductor substrate through successive layering of a gate oxide, a gate electrode and a gate cap oxide. A pair of curved gate spacer oxides are then formed covering opposite edges of the stack of the gate oxide, the gate electrode and the gate cap oxide. The semiconductor substrate is then etched to provide a smooth topographic transition from the gate spacer oxides to the etched semiconductor surface. Source/drain electrodes are then implanted into the etched semiconductor substrate and annealed to yield the finished transistor. A second embodiment of the field effect transistor possesses a polysilicon gate. Alter removal of the gate cap oxide, a metal layer may be deposited and sintered upon the polysilicon gate and the source/drain electrodes. The metal salicide layers formed upon the electrodes of the transistor have limited susceptibility to parasitic current leakage.

Abstract: A method of forming precisely cross-sectioned electron-transparent samples, includes removing, from a wafer, a chip containing a desired viewing site for analysis. At least one metallic mask is formed on a surface of the chip and over the viewing site using a focused ion beam microscope. Using a reactive ion etching technique, the chip is etched in a direction essentially perpendicular to the surface of the chip to form a thin viewing surface under the metallic mask. The thickness of the thin viewing surface is further reduced using a focused ion beam milling technique, to form an extremely thin electron-transparent sample.

Abstract: The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.

Abstract: A field effect transistor which is not susceptible to mask edge defects at its gate spacer oxides. The transistor is formed upon a (100) silicon semiconductor substrate through successive layering of a gate oxide, and a gate electrode. A pair of gate spacer oxides is then formed covering opposite edges of the gate oxide and the gate electrode. A screen oxide is then formed over the surface of the semiconductor substrate, the gate and the gate spacer oxides. The upper surface of the screen oxide has an angle of elevation not exceeding 54.44 degrees with respect to the semiconductor substrate. The screen oxide also smoothly flows from thicker regions at the junctures of the gate spacer oxides and the semiconductor substrate to thinner regions over the surface of the semiconductor substrate. The semiconductor substrate adjoining the gate spacer oxides is then ion implanted through the screen oxide to form amorphous source/drain electrodes.