Patents by Inventor Yong Feng Pan
Yong Feng Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10594704Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: GrantFiled: November 7, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Patent number: 10333947Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: GrantFiled: November 7, 2017Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Patent number: 10171482Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: GrantFiled: November 7, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Publication number: 20180097824Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: ApplicationFiled: November 7, 2017Publication date: April 5, 2018Inventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Publication number: 20180097823Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: ApplicationFiled: November 7, 2017Publication date: April 5, 2018Inventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Patent number: 9930052Abstract: A method for pattern matching finds a target pattern from a stream of patterns, both of the stream of patterns and the target pattern being comprised of elements. The method includes acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: GrantFiled: May 15, 2014Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Publication number: 20180069873Abstract: Pre-processing before precise pattern matching of a target pattern from a stream of patterns. Including acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: ApplicationFiled: November 7, 2017Publication date: March 8, 2018Inventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Patent number: 9443044Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.Type: GrantFiled: October 20, 2014Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Peng Fei Gou, Bodo Hoppe, Dan Liu, Yong Feng Pan
-
Publication number: 20150121323Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.Type: ApplicationFiled: October 20, 2014Publication date: April 30, 2015Inventors: Peng Fei Gou, Bodo Hoppe, Dan Liu, Yong Feng Pan
-
Publication number: 20150007320Abstract: A method for pattern matching finds a target pattern from a stream of patterns, both of the stream of patterns and the target pattern being comprised of elements. The method includes acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.Type: ApplicationFiled: May 15, 2014Publication date: January 1, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
-
Patent number: 8914574Abstract: The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item; searching the cache for presence of a row tag of the RAM data row corresponding to the data item of hash index; in response to presence, searching the RAM for a RAM data item corresponding to the input data item according to the corresponding row tag of the RAM data row; in response to absence, searching the RAM for a RAM data item corresponding to the input data item by using the data item of hash index; and in response to finding a RAM data item corresponding to the input data item in the RAM, outputting data corresponding to the RAM data item. The method can accelerate data search in the CAM.Type: GrantFiled: February 14, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Yong Feng Pan, Yufei Li, Bo Fan, Liang Chen
-
Patent number: 8490037Abstract: A method and an apparatus for tracking uncertain signals in the simulation of chip design are provided. The method comprises: generating a directed graph which contains sequential logic devices and IO devices from the netlist of chip design, wherein the directed graph illustrates the signal association among the sequential logic devices and IO devices; obtaining the signals related with the sequential logic devices and IO devices from the simulation results, wherein the signals contain a plurality of uncertain signals; and back tracing at least a part of the plurality of uncertain signals along the directed graph to determine the device which firstly generates an uncertain signal. The corresponding apparatus is also provided. With the above method and apparatus, uncertain signals can be traced and their source can be determined, which improves the debugging efficiency.Type: GrantFiled: October 25, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Liang Chen, Yufei Li, Yong Feng Pan, Jian Yang
-
Publication number: 20130046922Abstract: The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item; searching the cache for presence of a row tag of the RAM data row corresponding to the data item of hash index; in response to presence, searching the RAM for a RAM data item corresponding to the input data item according to the corresponding row tag of the RAM data row; in response to absence, searching the RAM for a RAM data item corresponding to the input data item by using the data item of hash index; and in response to finding a RAM data item corresponding to the input data item in the RAM, outputting data corresponding to the RAM data item. The method can accelerate data search in the CAM.Type: ApplicationFiled: February 14, 2012Publication date: February 21, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yong Feng Pan, Yufei Li, Bo Fan, Liang Chen
-
Publication number: 20120110526Abstract: A method and an apparatus for tracking uncertain signals in the simulation of chip design are provided. The method comprises: generating a directed graph which contains sequential logic devices and IO devices from the netlist of chip design, wherein the directed graph illustrates the signal association among the sequential logic devices and IO devices; obtaining the signals related with the sequential logic devices and IO devices from the simulation results, wherein the signals contain a plurality of uncertain signals; and back tracing at least a part of the plurality of uncertain signals along the directed graph to determine the device which firstly generates an uncertain signal. The corresponding apparatus is also provided. With the above method and apparatus, uncertain signals can be traced and their source can be determined, which improves the debugging efficiency.Type: ApplicationFiled: October 25, 2011Publication date: May 3, 2012Applicant: International Business Machines CorporationInventors: Liang Chen, Yufei Li, Yong Feng Pan, Jian Yang