Patents by Inventor Yong-Fong Lee
Yong-Fong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11507412Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.Type: GrantFiled: April 28, 2020Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Keqiang Wu, Jiwei Lu, Koichi Yamada, Yong-Fong Lee
-
Publication number: 20200319914Abstract: A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.Type: ApplicationFiled: April 28, 2020Publication date: October 8, 2020Inventors: Keqiang WU, Jiwei LU, Koichi YAMADA, Yong-Fong LEE
-
Patent number: 10761586Abstract: Systems, apparatuses and methods may provide for technology that determines a first real-time correlation between a power consumption of a processor and an operating frequency of the processor, determines a second real-time correlation between a performance level of the processor and the operating frequency of the processor, and sets the operating frequency of the processor to a value based on the first and second real-time correlations. In one example, the performance level or performance per watt of the processor decreases at one or more operating frequencies greater than the value.Type: GrantFiled: January 11, 2018Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Keqiang Wu, Yong-fong Lee, Krishnaswamy Viswanathan, Emad Guirguis
-
Patent number: 10642644Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.Type: GrantFiled: June 27, 2016Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Keqiang Wu, Jiwei Lu, Koichi Yamada, Yong-Fong Lee
-
Publication number: 20190041943Abstract: Systems, apparatuses and methods may provide for technology that determines a first real-time correlation between a power consumption of a processor and an operating frequency of the processor, determines a second real-time correlation between a performance level of the processor and the operating frequency of the processor, and sets the operating frequency of the processor to a value based on the first and second real-time correlations. In one example, the performance level or performance per watt of the processor decreases at one or more operating frequencies greater than the value.Type: ApplicationFiled: January 11, 2018Publication date: February 7, 2019Inventors: Keqiang Wu, Yong-fong Lee, Krishnaswamy Viswanathan, Emad Guirguis
-
Publication number: 20170371578Abstract: Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.Type: ApplicationFiled: June 27, 2016Publication date: December 28, 2017Inventors: Keqiang WU, Jiwei LU, Koichi YAMADA, Yong-Fong LEE
-
Patent number: 9411363Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.Type: GrantFiled: December 10, 2014Date of Patent: August 9, 2016Assignee: Intel CorporationInventors: Keqiang Wu, Jiwei Lu, Yong-Fong Lee
-
Publication number: 20160170438Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.Type: ApplicationFiled: December 10, 2014Publication date: June 16, 2016Inventors: Keqiang WU, Jiwei Lu, Yong-Fong Lee
-
Patent number: 9223699Abstract: Methods and apparatus to provide cache management in managed runtime environments are described. In one embodiment, a controller comprises logic to determine an update frequency for an object in the runtime environment and assigning the object to an unshared cache line when the update frequency exceeds an update frequency threshold. Other embodiments are also described.Type: GrantFiled: March 15, 2013Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Keqiang Wu, Kingsum Chow, Yong-Fong Lee
-
Publication number: 20140281230Abstract: Methods and apparatus to provide cache management in managed runtime environments are described. In one embodiment, a controller comprises logic to determine an update frequency for an object in the runtime environment and assigning the object to an unshared cache line when the update frequency exceeds an update frequency threshold. Other embodiments are also described.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Keqiang Wu, Kingsum Chow, Yong-Fong Lee
-
Patent number: 7437542Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.Type: GrantFiled: January 13, 2006Date of Patent: October 14, 2008Assignee: Intel CorporationInventors: Hong Wang, Ralph Kling, Yong-Fong Lee, David A. Berson, Michael A. Kozuch, Konrad Lai
-
Publication number: 20060155967Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.Type: ApplicationFiled: January 13, 2006Publication date: July 13, 2006Inventors: Hong Wang, Ralph Kling, Yong-Fong Lee, David Berson, Michael Kozuch, Konrad Lai
-
Patent number: 7051193Abstract: Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.Type: GrantFiled: March 28, 2001Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Hong Wang, Christopher J. Hughes, Ralph Kling, Yong-Fong Lee, Daniel M. Lavery, John Shen, Jamison Collins
-
Patent number: 7020766Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.Type: GrantFiled: May 30, 2000Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Hong Wang, Ralph Kling, Yong-Fong Lee, David A. Berson, Michael A. Kozuch, Konrad Lai
-
Publication number: 20050138340Abstract: A method and apparatus for selectively storing a register stack onto a register stack backing store is disclosed. In one embodiment, a non-exclusive boundary is determined enclosing registers that were actually used (e.g. written to) by a function. The description of that boundary is saved, and only the contents of the registers within the boundary are saved to register stack backing store as part of a spill operation. When the function is later restored, the description of the boundary is recalled and used to support the loading of just those registers from the register stack backing store as part of a fill operation.Type: ApplicationFiled: December 22, 2003Publication date: June 23, 2005Inventors: Yong-Fong Lee, Partha Kundu, Edward Grochowski
-
Patent number: 6848043Abstract: Methods and apparatus for improving system performance using redundant arithmetic are disclosed. In one embodiment, one or more dependency chains are formed. A dependency chain may comprise of two or more instructions. A first instruction may generate a result in a redundant form. A second instruction may accept the result from the first instruction as a first input operand. The instructions in the dependency chain may execute separately from instructions not in the dependency chain.Type: GrantFiled: April 27, 2000Date of Patent: January 25, 2005Assignee: Intel CorporationInventors: Thomas Y. Yeh, Hong Wang, Ralph Kling, Yong-Fong Lee
-
Publication number: 20020144101Abstract: A DAG trace cache includes traces, each storing information about interdependent instructions and the interdependency among the instructions. The interdependent instructions include a criterion instruction and are part of a program sequence that is stored in an instruction cache. The information is in the form of a directed acyclic graph. The interdependent instructions include the criterion instruction and instructions preceding the criterion instruction in the program sequence. The information in the DAG trace is used to accelerate executions of the instructions on a processor.Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Inventors: Hong Wang, Neil A. Chazin, Christopher J. Hughes, Ralph Kling, John Shen, Yong-Fong Lee
-
Publication number: 20020144098Abstract: Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.Type: ApplicationFiled: March 28, 2001Publication date: October 3, 2002Applicant: Intel CorporationInventors: Hong Wang, Christopher J. Hughes, Ralph Kling, Yong-Fong Lee, Daniel M. Lavery, John Shen, Jamison Collins
-
Patent number: 6202204Abstract: In one implementation of the invention, a computer implemented method used in compiling a program includes identifying a covering load, which may be one of a set of covering loads, and a redundant load. The covering load and the redundant load have a first and second load type, respectively. The first and the second load type each may be one of a group of load types including a regular load and at least one speculative-type load. In one implementation, the group of load types includes at least one check-type load. One implementation of the invention is in a machine readable medium.Type: GrantFiled: March 11, 1998Date of Patent: March 13, 2001Assignee: Intel CorporationInventors: Youfeng Wu, Yong-Fong Lee