Abstract: Embodiments of the present disclosure provide a memory system, and a method for garbage collection of the memory system. The method can include reading N valid data sets in a to-be-collected virtual block (VB) of a memory out to a copy buffer sequentially, where N is an integer greater than or equal to 2, transferring a valid data set in the copy buffer to a corresponding cache, and reading a next valid data set out to the copy buffer, and programming the valid data set in the cache to a corresponding target die group of a target VB. A time period in which a current valid data set is programmed from the cache to the target die group corresponding to the cache overlaps at least partially with a time period in which a next valid data set is read from the to-be-collected VB to the copy buffer.

Abstract: Systems and methods of synthesizing nanoparticles on substrates using rapid, high temperature thermal shock. A method involves depositing micro-sized particles or salt precursors on a substrate, and applying a rapid, high temperature thermal pulse or shock to the micro-sized particles or the salt precursors and the substrate to cause the micro-sized particles or the salt precursors to become nanoparticles on the substrate. A system may include a rotatable member that receives a roll of a substrate sheet having micro-sized particles or salt precursors; a motor that rotates the rotatable member so as to unroll consecutive portions of the substrate sheet from the roll; and a thermal energy source that applies a short, high temperature thermal shock to consecutive portions of the substrate sheet that are unrolled from the roll by rotating the first rotatable member. Some systems and methods produce nanoparticles on existing substrate.

Abstract: An electronic equipment accessory includes an accessory body and a holder assembly connected to the accessory body. The holder assembly includes a support member and a base. The base is rotatably connected to the accessory body. The support member is rotatable relative to the base between an extended position and a folded position. At the extended position, an included angle is formed between the support member and the base to thereby allow the accessory body to be supported on a support surface. The support member is rotatable relative to the base in one direction and the base is rotatable relative to the accessory body in another direction, thus the support member of the electronic equipment accessory can be adjusted with respect to the accessory body in multiple directions to thereby allow the electronic equipment accessory to support electronic equipment on a support surface at multiple different directions or tilted angles.

Abstract: A brake upper pump with an adjustable force arm, including a brake pump body, a brake handle, and a piston rod components extending into the brake pump body; The position where the user holds the brake lever is the grip input position, the connection between the brake pump body and the brake lever is the rotation fulcrum position, the connection between the piston rod assembly and the brake lever is the thrust output position; The distance between the rotation fulcrum position and the force-generating point of the user's hand-held brake lever forms the input force arm, and the distance between the rotation fulcrum position and the thrust output position forms the output force arm; A first force arm adjustable mechanism is provided at the rotation fulcrum, and the first force arm adjustable mechanism can change the rotation center of the brake lever relative to the brake pump body.

Abstract: The present application relates to the technical field of pulse ablation, in particular to an electric pulse ablatograph for an endoscope, which includes: an electrode assembly including a central electrode and a cylindrical electrode and configured to pass through a working channel of the endoscope into a body and transmit a pulse to tissues in use; a pulse waveform generator coupled to the electrode assembly and configured to transmit pulse voltage to the electrode assembly; an electrode driving device configured to drive the central electrode and the cylindrical electrode; a parameter input device configured to configure coordinate information of an ablation region; and a control device in signal connection with the parameter input device and in control connection with the electrode driving device.

Abstract: A control system includes an electric pulse host including control and feedback circuits, and an electrode group. The control circuit includes a main control module (MCM) connected with a pulse transmission module, a first electrode control unit and the electrode group. The MCM controls the pulse transmission module to output a pulse signal and selects a specific electrode through the first electrode control unit to release the pulse signal to act on an ablation site. The feedback circuit includes the MCM connected with an electrophysiological signal sampling module, a second electrode control unit and the electrode group. The MCM selects an electrode through the second electrode control unit, samples an electrocardiogram signal through the electrophysiological signal sampling module, determines a treatment progress according to the sampled electrocardiogram signal, and adjusts the pulse signal output by the pulse transmission module in real time according to the treatment progress.

Abstract: A Hydraulic Brake with Dual Piston Structure includes a brake body, a handle, and a brake oil pipe; the brake body is provided with a pressure cylinder and a reservoir, and the pressure cylinder is provided with a piston assembly acted by the handle, and the pressure cylinder is connected to the reservoir through an oil pressure regulating hole. The piston assembly includes a front piston rod and a rear piston rod. The rear piston rod is provided with a push cavity, and the front piston rod is capable of entering the push cavity; an oil guiding cavity and an overflow hole in communication are provided on the front piston rod. The front piston rod is also sleeved with a one-way oil seal in contact with the inner wall of the pressure cylinder. The one-way oil seal is located in front of the overflow hole.

Abstract: A system and a method for evaluating transmission performance related to a network node, and a related device are disclosed. The system includes a network node and a control node. The network node is configured to obtain a test packet, and process the test packet by using a virtual switch, to generate a mirrored packet corresponding to the test packet. The mirrored packet carries a generation timestamp and generation location information. The control node is configured to receive the mirrored packet from the network node, to evaluate, based on the mirrored packet, transmission performance of at least a part of link that is related to the network node and that is in a path. The control node obtain transmission performance of the network node in the path and the transmission performance of at least a part of link that is related to the network node.

Abstract: The present disclosure provides a system. The system includes a memory device and a controller. The memory device is configured to store memory data and includes a plurality of memory modules. Each of the memory modules includes a first memory block and a second memory block. The controller includes a processor and a memory. The controller is operatively coupled to the plurality of memory modules. In an operation on redundant array of independent disks (RAID), the controller is configured to generate a first check code based on memory data in the first memory block of the plurality memory modules, generate a second check code based on memory data in the second memory block of the plurality memory modules, and generate an additional check code based on the first check code and the second check code.

Abstract: A system includes a memory device configured to store memory data. The memory device includes a plurality of valid memory blocks. The system also includes a controller coupled to the plurality of valid memory blocks. The controller is configured to, in response to data stored in one valid memory block of the plurality of valid memory blocks being lost, restore the data stored in the one valid memory block based on a check factor comprising a first address pointer pointing to the penultimate valid memory block successfully written and a second address pointer pointing to the last valid memory block successfully written.

Abstract: This application discloses a packet loss management method. The method includes: A controller determines, based on a network quality requirement of service traffic and a network quality parameter of each segment link on a forwarding path of the service traffic, a packet loss concealment policy that needs to be executed on each segment link on the forwarding path, and delivers the packet loss concealment policy for each segment link to a forwarding node, and the forwarding node executes the corresponding packet loss concealment policy.

Abstract: The present invention relates to efficient synthetic processes useful in the preparation of Compound A, a BTK inhibitor of Formula (I): or a pharmaceutically acceptable salt thereof, including the preparation of intermediates used to make Compound A or a pharmaceutically acceptable salt thereof.

Abstract: The present disclosure provides a system. The system includes a memory device configured to store memory data. The memory device includes a plurality of valid memory blocks that comprises a first valid memory block and a second valid memory block. The system also includes a controller, having a processor and a memory, operatively coupled to the first and second valid memory blocks. The controller is configured to, in an operation on redundant array of independent disks (RAID), generate an address chain in a check code factor of the plurality of valid memory blocks, the address chain comprising a first address point pointing to the first valid memory block. The controller is also configured to generate, in the first valid memory block, a second address pointer, the second address pointer pointing to the second valid memory block.

Abstract: Disclosed herein is a hydraulic brake with travel adjustment mechanism, comprising a brake body with a pressure cylinder; a piston rod extending through the pressure cylinder; a lever; a spring connected between the piston rod and the pressure cylinder; a brake hose connected to the other end of the brake body; a connecting rod, one end of which is connected to the lever, and the other end of which extends through the pressure cylinder to form a transmission engagement with the piston rod, a limiting component is arranged inside the pressure cylinder, and the limiting component acts on the connecting rod to restrict the connecting rod from leaving the pressure cylinder; an adjustable chamber is arranged in the connecting rod, and an adjustment element is provided inside the adjustable chamber, one end of which extends out of the adjustable chamber and forms a transmission engagement with the piston rod.

Abstract: Embodiments of the present disclosure provide a memory system, and a method for garbage collection of the memory system. The method can include reading N valid data sets in a to-be-collected virtual block (VB) of a memory out to a copy buffer sequentially, where N is an integer greater than or equal to 2, transferring a valid data set in the copy buffer to a corresponding cache, and reading a next valid data set out to the copy buffer, and programming the valid data set in the cache to a corresponding target die group of a target VB. A time period in which a current valid data set is programmed from the cache to the target die group corresponding to the cache overlaps at least partially with a time period in which a next valid data set is read from the to-be-collected VB to the copy buffer.

Abstract: The present disclosure provides a successive approximation method of three-state quantization and a successive approximation analog-to-digital converter circuit. The method includes for a first successive approximation of the arbitrary analog input signal between 0 and 1, comparing it with a quantization line 1/2; performing a second successive approximation according to a state of the first successive approximation; and by analogy up to a Nth successive approximation, in case that a certain successive approximation is the state three during the comparison process, ending the approximation, indicating that the interval where the signal is located has been found.

Abstract: Provided is a heterocycle substituted ketone derivative, the structure of which is as shown in formula (I). Further provided are a pharmaceutically acceptable salt of the derivative, a stereoisomer thereof, a pharmaceutical composition and the medicinal use thereof.

Abstract: A fishing reel that is easy to switch with one hand, comprising a fishing reel frame; a fishing reel line spool, which is rotatably connected to the fishing reel frame for retrieving and releasing the fishing line; a fishing reel handle, which is located on the side where the fishing reel line spool is located; a transmission component, which is provided between the fishing reel handle and the fishing reel line spool; a clutch component, which acts on the transmission component. The clutch component comprises a clutch lever, which extends at least partially out of the fishing reel frame and is located on the side of the fishing reel frame away from the fishing reel handle.

Abstract: The present disclosure provides a system. The system includes a memory device configured to store memory data. The memory device includes a plurality of valid memory blocks that comprises a first valid memory block and a second valid memory block. The system also includes a controller, having a processor and a memory, operatively coupled to the first and second valid memory blocks. The controller is configured to, in an operation on redundant array of independent disks (RAID), generate an address chain in a check code factor of the plurality of valid memory blocks, the address chain comprising a first address point pointing to the first valid memory block. The controller is also configured to generate, in the first valid memory block, a second address pointer, the second address pointer pointing to the second valid memory block.

Abstract: The present disclosure provides a system. The system includes a memory device and a controller. The memory device is configured to store memory data and includes a plurality of memory modules. Each of the memory modules includes a first memory block and a second memory block. The controller includes a processor and a memory. The controller is operatively coupled to the plurality of memory modules. In an operation on redundant array of independent disks (RAID), the controller is configured to generate a first check code based on memory data in the first memory block of the plurality memory modules, generate a second check code based on memory data in the second memory block of the plurality memory modules, and generate an additional check code based on the first check code and the second check code.