Abstract: The present invention relates to a catalyst for hydrogenation and a method for preparing the same, and more specifically, provides a catalyst having improved activity by including copper and copper oxide as a promoter when a hydrogenation catalyst including nickel is prepared by using a deposition-precipitation (DP) method. Accordingly, a catalyst having high activity may be provided in a hydrogenation process of a hydrocarbon resin.

Abstract: The present invention relates to: a negative electrode active material including silicon-based composite particles containing SiOx (0<x<2) and a MgSiO3 phase, wherein the MgSiO3 phase includes a first MgSiO3 phase having an enstatite structure and a second MgSiO3 phase having a clinoenstatite structure at a weight ratio of 1:1 to 1:5; a negative electrode including the same; and a secondary battery including the negative electrode.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Abstract: The present disclosure relates to an apparatus and method for fast refining segmentation for a V-PCC encoder. The apparatus may include a grid segmentation unit segmenting a coordinate space of a point cloud into grid units, and an edge cube search unit searching a cube containing one or more points among the cubes segmented into grid units and containing a segment boundary. The apparatus may also include a surrounding cube search unit searching an edge surrounding cube containing one or more points within a predetermined range from the edge cube, and a smooth score calculation unit calculating smooth scores for all the edge surrounding cubes and all the edge cubes. The apparatus may further include a projection plane index update unit obtaining a normal score based on the calculated smooth scores and updating a projection plane index of each point in the edge cube using the normal score.

Abstract: A device and method for performing fast grid-based refining segmentation (FGRS) for video-based point cloud compression (V-PCC) is proposed. The method may include dividing a space of a three-dimensional (3D) point cloud into multiple grids to derive multiple voxels, searching for filled voxels including one or more points, searching for surrounding voxels which are filled voxels within a certain radius from each of the filled voxels, and searching for edge voxels which are present at a segment edge among all the filled voxels. The method may also include calculating smooth scores for surrounding voxels of each edge voxel and calculating a smooth score sum which is a smooth score for the edge voxel on the basis of the smooth scores of the surrounding voxels of the edge voxel, and updating a projection plane index (PPI) for each individual point in the edge voxel using the calculated smooth score sum.

Abstract: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Abstract: A hi-fix board, a test tray, a test handler, and a packaged chip manufacturing method are provided. The hi-fix board includes: test sockets to which packaged chips to be tested are connected; and a main frame in which the test sockets are disposed in at least one first area to form an a×b matrix (where a and b are integers greater than 0) and the test sockets are disposed in at least one second area to form a c×d matrix (where c is an integer greater than a and d is an integer greater than 0). By allowing the test tray to contain more packaged chips at a time and minimizing a difference in length between a horizontal direction and a vertical direction, it is possible to reduce the index time. By allowing all the packaged chips contained in a test tray to be subjected to a testing process at the same time, it is possible to reduce the time for the testing process and to enhance the stability.

Abstract: Provided is a sorting system for handling packaged chips for testing and sorting the packaged chips by grade, capable of performing loading and unloading operations, independently of a testing operation. The sorting system includes a loading unit including a loading picker, an unloading unit provided adjacent to the loading unit, a rack in which to store at least one test tray containing the packaged chips intended for the tests and at least one test tray containing the tested packaged chips, an exchanging site where the test tray containing the packaged chips intended for the tests and the test tray containing the tested packaged chips are exchanged with the rack, and a transferring unit transferring the test tray between the loading position, the exchanging site, and the unloading position.

Abstract: Provided is a method for transferring test trays in a handler including a second chamber having two test sites arranged in parallel, a first chamber having a plurality of passages along which a plurality of test trays are horizontally moved, provided over the second chamber, and a third chamber having a plurality of passages along which the plurality of test trays are horizontally moved, provided under the second chamber, the method including steps of (a) enabling two test trays to wait in parallel in a horizontal position at a waiting location provided to a forward section of the handler, (b) loading packaged chips onto the two test trays, (c) rotating the two test trays to be in the upright position, (d) moving upwards the two test trays into the first chamber, (e) heating or cooling the two test trays while moving horizontally the two test trays forward in the first chamber, (f) moving downward the two test trays from the first chamber into the second chamber, (g) moving horizontally the two test trays tow