Abstract: Display panel driving circuits and methods of driving a display panel with first video data and second video data include determining a starting position and a stopping position of the first video data if the first video data is window data and reducing the size of the first video data if the first video data is full screen data. Alternating lines of a first portion of the display panel and a second portion of the display panel are driven with the reduced size first video data and the second video data so as to display the reduced size first video data in the first portion of the display panel and the second video data in the second portion of the display panel if the first video data is full screen data.

Abstract: A method of restoring RGB gray scale data for maintaining a sharpness of a screen and reducing a size of a memory is disclosed. The RGB gray scale data having M bits are truncated to generate a first RGB gray scale data having N bits, M being a positive integer and N being an integer less than M. RGB gray scale data information is generated based on a bit information of the first RGB gray scale data. A bit value of a MSB of the first RGB gray scale data is compared with a value of a dither table based on the RGB gray scale data information to generate a comparison value, when a bit value of at least one bit of the first RGB gray scale data is different from other bit values of the first RGB gray scale data. The first RGB gray scale data are compensated based on the RGB gray scale data information and the comparison value. Thus, the sharpness of a screen may be maintained and the size of the memory may be reduced.

Abstract: Image data and/or On-Screen Display (OSD) data is generated for display on a display having rows of pixels by repeatedly combining a portion of the OSD data and a portion of the display data in a display driver chip without storing more than the portion of the display data and/or the portion of the OSD data in the display driver chip at any time. The driver chip memory thereby may be reduced.

Abstract: Provided are a source driver and a source line driving method using a gamma driving scheme for a liquid crystal display (LCD) device. The source driver for driving the LCD device encodes serially input red (R), green (G), and blue (B) digital image data during a horizontal scan period, stores the encoded values of the R, G, and B digital image data in a first memory, and turns on or off grayscale voltage amplifiers included in a gamma voltage amplifying unit according to the encoded values stored in the first memory. Accordingly, when an output selecting unit selects a corresponding grayscale voltage output from the gamma voltage amplifying unit, and outputs the selected voltage to each source line, only the amplifiers necessary for driving a liquid crystal panel are turned on.

Abstract: For driving dual display panels, one of first and second display panels is determined to be a display mode panel, and the other one of the display panels is determined to be a non-display mode panel. Image data is displayed on the display mode panel, and the image data is stored in a same shared memory for when the display mode panel is either one of the first and second display panels. In addition, the non-display mode panel is driven in a selected one of a black display mode or a white display mode every predetermined frame interval for reducing noise.

Abstract: Display panel driving circuits and methods of driving a display panel with first video data and second video data include determining a starting position and a stopping position of the first video data if the first video data is window data and reducing the size of the first video data if the first video data is full screen data. Alternating lines of a first portion of the display panel and a second portion of the display panel are driven with the reduced size first video data and the second video data so as to display the reduced size first video data in the first portion of the display panel and the second video data in the second portion of the display panel if the first video data is full screen data.

Abstract: A method of restoring RGB gray scale data for maintaining a sharpness of a screen and reducing a size of a memory is disclosed. The RGB gray scale data having M bits are truncated to generate a first RGB gray scale data having N bits, M being a positive integer and N being an integer less than M. RGB gray scale data information is generated based on a bit information of the first RGB gray scale data. A bit value of a MSB of the first RGB gray scale data is compared with a value of a dither table based on the RGB gray scale data information to generate a comparison value, when a bit value of at least one bit of the first RGB gray scale data is different from other bit values of the first RGB gray scale data. The first RGB gray scale data are compensated based on the RGB gray scale data information and the comparison value. Thus, the sharpness of a screen may be maintained and the size of the memory may be reduced.

Abstract: A DMA controller includes a burst/single mode control circuit for automatically converting a DMA transfer operation mode to a burst mode and/or a single mode regardless of a data transfer counter value, and for performing the DMA transfer operation. The burst/single mode control circuit carries out the burst mode DMA transfer operation without the need for a control operation of the CPU a number of times corresponding to a quotient which is the result that the data transfer counter value divided by the burst length, and carries out successively the single mode DMA transfer operation by the number of times corresponding to the remainder of the division.

Abstract: A DMA controller includes a burst/single mode control circuit for automatically converting a DMA transfer operation mode to a burst mode and/or a single mode regardless of a data transfer counter value, and for performing the DMA transfer operation. The burst/single mode control circuit carries out the burst mode DMA transfer operation without the need for a control operation of the CPU a number of times corresponding to a quotient which is the result that the data transfer counter value divided by the burst length, and carries out successively the single mode DMA transfer operation by the number of times corresponding to the remainder of the division.