Abstract: A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.

Abstract: A memory controller transmits one or more command pairs of a self-refresh entry command and a subsequent self-refresh exit command to a semiconductor memory device during a refresh period. The semiconductor memory device includes a memory cell array including a plurality of memory cell rows each including a plurality of dynamic memory cells, and a refresh control circuit. The refresh control circuit performs a refresh operation on all of the memory cell rows during the refresh period in a self-refresh mode, the self-refresh mode of the refresh period being configured in response to each self-refresh entry command of the one or more command pairs, for each of the one or more command pairs, the memory controller sequentially transmits during the refresh period at least one self-refresh entry command and at least one self-refresh exit command to the semiconductor memory device separated by one or more time gaps.

Abstract: An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.

Abstract: An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.

Abstract: A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

Abstract: A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.

Abstract: The semiconductor device may include a calibration circuit, a control unit, and a delay unit. The calibration circuit may be configured to output an output signal. The control unit may be configured to generate and output the control signal in response to the output signal of the calibration circuit. The control unit may generate the control signal by using a correlation between a signal transmission speed of the semiconductor device and the output signal of the calibration circuit. The delay unit may be configured to delay a clock signal in response to the control signal and output the delayed clock signal to the output driver.

Abstract: A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output buffer outputting cell data amplified by the peripheral circuit. The output buffer includes an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device, and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal.

Abstract: A semiconductor device has at least two semiconductor memory devices, each of which includes a memory cell array arranged in a matrix of rows and columns, a peripheral circuit writing data to a cell of the memory cell array and reading out and amplifying the written data, and an output buffer outputting cell data amplified by the peripheral circuit. The output buffer includes an output buffer initialization circuit activating an output buffer reset signal in response to the power up or power down of the semiconductor memory device and deactivating the output buffer reset signal in response to a first command signal output from a controller of the semiconductor memory device, and an output driver generating output data based on a data signal in response to a clock signal, a data enable signal, and the output buffer reset signal.

Abstract: A memory system that includes a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register and delay circuit unit for outputting command/address output signals after receiving the command/address input signals front the controller and then correcting transmission delay due to transmission lines; wherein the plurality of memory devices receive the command/address output signals from the register and delay circuit unit via the transmission lines, respectively, and sample the command/address output signals using the first clock signal directly inputted from the controller. As a result, the memory system can simplify the layout of semiconductor device design and prevent the collision of clocks.

Abstract: The present invention generally relates to memory system wherein clocks for sampling command and address signals are removed. The memory system comprising a plurality of memory devices includes: a controller for outputting a first clock signal, a second signal and a plurality of command/address input signals corresponding to the plurality of memory devices, respectively; and a register and delay circuit unit for outputting command/address output signals after receiving the command/address input signals from the controller and then correcting transmission delay due to transmission lines; wherein the plurality of memory devices receive the circuit unit via the transmission lines, respectively, and simple the command/address output signals using the first clock signal directly inputted from the controller. As a result, the memory system according to the present invention can simplify the layout of semiconductor device design and prevent the collision of clocks.

Abstract: The present invention relates to a multiple data rate memory device which has broadened the concept of a double data rate SDRAM. The multiple data rate memory device includes clock signal generator means for receiving an external clock of a frequency f and outputting a plurality of clocks, a frequecy multi-doubler for logically operating the plurality of clocks and outputting an internal clock of a frequency 2Nf (N is natural number); an odd data input buffer for receiving tha data at the rising edge of the internal clock; and an even data input buffer for receiving tha data at the falling edge of the internal clock.

Abstract: A sense amplifier enable signal generator for a semiconductor memory device, comprising a counter for generating a pulse signal synchronously with a clock signal when a row address strobe bar signal is made active and suppressing the generation of the pulse signal when the row address strobe bar signal is disabled, and a comparator for generating a sense amplifier enable signal when an output value from the counter reaches a predetermined time delay value and suppressing the generation of the sense amplifier enable signal when the row address strobe bar signal is disabled. According to the present invention, a sense amplifier can be operated at a proper time without being affected by a process parameter, an operating voltage, temperature, etc.