Patents by Inventor Yong Han Jeon
Yong Han Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11778741Abstract: A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second portion having an upper surface higher than the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on an upper surface of a first region of the insulating layer, and a plurality of second circuit patterns disposed on an upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than an upper surface of the first circuitType: GrantFiled: March 12, 2021Date of Patent: October 3, 2023Assignee: LG INNOTEK CO., LTD.Inventors: Yong Han Jeon, Jin Seok Lee, Tae Ki Kim
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Publication number: 20230113302Abstract: A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second.Type: ApplicationFiled: March 12, 2021Publication date: April 13, 2023Inventors: Yong Han JEON, Jin Seok LEE, Tae Ki KIM
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Patent number: 11257985Abstract: A semiconductor device disclosed in an embodiment comprises: a light emitting unit comprising a light emitting structure layer which has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a sensor unit disposed on the light emitting unit, wherein the sensor unit comprises: a sensing material changing in resistance with light emitted by the light emitting unit; a first sensor electrode comprising a first pad portion and a first extension part extending from the first pad portion and contacting the sensing material; and a second sensor electrode comprising a first pad portion and a second extension part extending toward the first extension part from the second pad portion and contacting the sensing material. The sensor unit senses an external gas in response to the light generated from the light emitting unit.Type: GrantFiled: December 4, 2017Date of Patent: February 22, 2022Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.Inventors: Deok Ki Hwang, Jae Hun Jeong, Ki Bum Sung, Sang Jun Park, Tae Yong Lee, Yong Han Jeon
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Publication number: 20200066936Abstract: A semiconductor device disclosed in an embodiment comprises: a light emitting unit comprising a light emitting structure layer which has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a sensor unit disposed on the light emitting unit, wherein the sensor unit comprises: a sensing material changing in resistance with light emitted by the light emitting unit; a first sensor electrode comprising a first pad portion and a first extension part extending from the first pad portion and contacting the sensing material; and a second sensor electrode comprising a first pad portion and a second extension part extending toward the first extension part from the second pad portion and contacting the sensing material. The sensor unit senses an external gas in response to the light generated from the light emitting unit.Type: ApplicationFiled: December 4, 2017Publication date: February 27, 2020Applicant: LG INNOTEK CO., LTD.Inventors: Deok Ki HWANG, Jae Hun JEONG, Ki Bum SUNG, Sang Jun PARK, Tae Yong LEE, Yong Han JEON
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Publication number: 20170324004Abstract: Disclosed is a light emitting device according to the embodiment including a conductive semiconductor layer divided into at least two or more light emitting regions; a plurality of light emitting structures on the conductive semiconductor layer; an electrode layer on the plurality of light emitting structures; a second electrode electrically connected to the electrode layer; and a first electrode electrically connected to the conductive semiconductor layer, wherein each of the light emitting structures includes a rod-shaped first conductivity type semiconductor, an active layer configured to surround the first conductivity type semiconductor and a second conductivity type semiconductor configured to surround the active layer, and each of the light emitting structures has at least two or more outer surfaces having different extending directions with respect to an upper surface of the conductive semiconductor layer.Type: ApplicationFiled: October 29, 2015Publication date: November 9, 2017Applicant: LG INNOTEK CO., LTD.Inventors: Eun Hyung LEE, Yoo Hwan KANG, Won Ho KIM, Tae Ki KIM, Sungwon David ROH, Hyo Jung MOON, Yong Han JEON
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Publication number: 20120129321Abstract: A semiconductor device manufacturing apparatus includes a chamber including a reaction space, a substrate disposing unit configured to dispose a substrate within the chamber, a first heating unit configured to optically heat the reaction space and disposed under the chamber, a second heating unit configured to heat the reaction space through resistive heating and disposed over the chamber, and a plasma generating unit configured to generate plasma in the reaction space. Since the apparatus generates the plasma using the plasma generating unit disposed over the chamber, the deposition process based on heating and the etch process based on the plasma can be simultaneously performed in one single chamber.Type: ApplicationFiled: January 30, 2012Publication date: May 24, 2012Applicant: JUSUNG ENGINEERING CO., LTDInventors: Cheol Hoon YANG, Kyu Jin CHOI, Yong Han JEON, Euy Kyu LEE, Tae Wan LEE
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Patent number: 8168505Abstract: A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.Type: GrantFiled: May 13, 2011Date of Patent: May 1, 2012Assignee: Jusung Engineering Co., Ltd.Inventors: Cheol Hoon Yang, Yong Han Jeon
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Publication number: 20110212604Abstract: A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.Type: ApplicationFiled: May 13, 2011Publication date: September 1, 2011Applicant: Jusung Engineering CO., LTD.Inventors: Cheol Hoon YANG, Yong Han JEON
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Patent number: 7943969Abstract: A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.Type: GrantFiled: October 27, 2008Date of Patent: May 17, 2011Assignee: Jusung Engineering Co. Ltd.Inventors: Cheol Hoon Yang, Yong Han Jeon
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Publication number: 20100101730Abstract: A substrate processing apparatus, which is designed to prevent the wobbling of a rotational shaft rotating, is provided. The substrate includes a rotation shaft and a connecting member. A unit is disposed between the rotational shaft and the connecting member to make the rotational shaft and the connecting member close-contact each other or a unit is disposed under the rotational shaft to prevent the wobbling of the rotational shaft.Type: ApplicationFiled: October 21, 2009Publication date: April 29, 2010Applicant: JUSUNG ENGINEERING CO., LTD.Inventors: Kyu Jin CHOI, Sung Min NA, Euy Kyu LEE, Yong Han JEON, Cheol Hoon YANG, Tae Wan LEE, Uk HWANG, Sun Kee KIM
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Publication number: 20100006539Abstract: A semiconductor device manufacturing apparatus includes a chamber including a reaction space, a substrate disposing unit configured to dispose a substrate within the chamber, a first heating unit configured to optically heat the reaction space and disposed under the chamber, a second heating unit configured to heat the reaction space through resistive heating and disposed over the chamber, and a plasma generating unit configured to generate plasma in the reaction space. Since the apparatus generates the plasma using the plasma generating unit disposed over the chamber, the deposition process based on heating and the etch process based on the plasma can be simultaneously performed in one single chamber.Type: ApplicationFiled: October 27, 2008Publication date: January 14, 2010Applicant: JUSUNG ENGINEERING CO., LTDInventors: Cheol Hoon YANG, Kyu Jin CHOI, Yong Han JEON, Euy Kyu LEE, Tae Wan LEE
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Publication number: 20090108308Abstract: A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.Type: ApplicationFiled: October 27, 2008Publication date: April 30, 2009Applicant: JUSUNG ENGINEERING CO., LTDInventors: Cheol Hoon YANG, Yong Han JEON
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Patent number: 6104855Abstract: A terminal assembly for an optic cable equipped with terminal connectors is provided with a housing having a small through-hole and a large through-hole. A plug for keeping optical fibers within the housing to prevent the optical fibers from getting entangled with one another is mounted within the housing. Through the use of a nut member fixed to the cable, the housing is fixed to the cable. A flexible cap member for enclosing the optical fibers and the terminal connectors is combined with the housing to enclose them.Type: GrantFiled: September 30, 1998Date of Patent: August 15, 2000Assignee: Daewoo Telecom Ltd.Inventor: Yong Han Jeon