Abstract: A synthetic test circuit for testing a submodule performance in a power compensator includes a submodule test unit which is an object of testing the submodule performance, a current source and a controller. The current source is connected to the submodule test unit to supply a voltage to the submodule test unit such that a charging voltage having a capacity set in the submodule test unit is stored in order to operate the submodule test unit. The controller is configured to perform control to perform a submodule performance test of the submodule test unit using the stored charging voltage.

Abstract: A reactive power compensator includes a plurality of phase clusters each including plurality of cells and a controller configured to control the plurality of phase clusters. The controller performs control to generate an offset signal through phasor transformation based on respective voltage values and current values of the plurality of phase clusters and to compensate for energy errors between the plurality of phase clusters based on the generated offset signal.

Abstract: A reactive power compensator includes a plurality of phase clusters each including a plurality of cells, and a controller configured to control the plurality of phase clusters. When an energy error is generated in each of the plurality of phase clusters, the controller performs control to compensate for the energy error by generating an offset signal having a zero sequence component based on an error energy value of each of the plurality of phase clusters.

Abstract: A reactive power compensator includes a plurality of phase clusters each including plurality of cells and a controller configured to control the plurality of phase clusters. The controller performs control to generate an offset signal through phasor transformation based on respective voltage values and current values of the plurality of phase clusters and to compensate for energy errors between the plurality of phase clusters based on the generated offset signal.

Abstract: A reactive power compensator includes a plurality of phase clusters each including a plurality of cells, and a controller configured to control the plurality of phase clusters. When an energy error is generated in each of the plurality of phase clusters, the controller performs control to compensate for the energy error by generating an offset signal having a zero sequence component based on an error energy value of each of the plurality of phase clusters.

Abstract: A power supply system includes: an electricity generation device configured to generate electrical energy; a plurality of DC/AC converters configured to convert the electrical energy into AC; and a battery energy storage system (BESS) configured to receive and charge the electrical energy and supplies the electrical energy to the plurality of DC/AC converters by discharging the charged electrical energy. The electrical energy generated by the electricity generation device charges the BESS without going through the plurality of DC/AC converters.

Abstract: A reactive power compensation apparatus includes one or more phase clusters each comprising a plurality of cells, and a controller controlling the one or more phase clusters. When at least one cell in a specific phase cluster among the one or more phase clusters is faulty, the controller controls a voltage of each cell in each of the remaining phase clusters except for the specific phase cluster to be controlled, using a modulation index.

Abstract: A reactive power compensation apparatus includes one or more phase clusters each comprising a plurality of cells, and a controller controlling the one or more phase clusters. When at least one cell in a specific phase cluster among the one or more phase clusters is faulty, the controller controls a voltage of each cell in each of the remaining phase clusters except for the specific phase cluster to be controlled, using a modulation index.

Abstract: A synthetic test circuit for testing a submodule performance in a power compensator includes a submodule test unit which is an object of testing the submodule performance, a current source and a controller. The current source is connected to the submodule test unit to supply a voltage to the submodule test unit such that a charging voltage having a capacity set in the submodule test unit is stored in order to operate the submodule test unit. The controller is configured to perform control to perform a submodule performance test of the submodule test unit using the stored charging voltage.

Abstract: The present disclosure relates a modular multi-level converter (MMC) including two arms including different types of sub modules according to the respective arms, two sub controllers corresponding to the two arms, respectively and configured to separately control the two arms, respectively, and a central controller configured to determine a switching operation condition of the sub module and to output a switching signal corresponding to the switching operation condition to each of the two sub controllers, wherein the two sub controllers control the respective corresponding arms based on the switching signal and, upon receiving a voltage change switching signal for controlling a voltage applied to one of the two arms, change the voltage applied to one of the two arms based on the voltage change switching signal.

Abstract: Embodiments of a synthetic test circuit for a valve performance test of high-voltage direct current (HVDC) are presented. In some embodiments, the synthetic test circuit comprises a resonance circuit configured to comprise a first test valve to test an operation of an inverter mode and a second test valve to test an operation of a rectifier mode. The synthetic test circuit may comprise a power supply (P/S) configured to provide the resonance circuit with an operating voltage. The synthetic test circuit may comprise a direct current/direct current (DC/DC) converter configured to bypass a DC offset current of the resonance circuit. The first test valve may be an inverter unit, which may have a positive DC current offset. Further, the second test valve may be a rectifier unit, which may have a negative DC current offset.

Abstract: Embodiments of a synthetic test circuit for a valve performance test of high-voltage direct current (HVDC) are presented. In some embodiments, the synthetic test circuit comprises a resonance circuit configured to comprise a first test valve to test an operation of an inverter mode and a second test valve to test an operation of a rectifier mode. The synthetic test circuit may comprise a power supply (P/S) configured to provide the resonance circuit with an operating voltage. The synthetic test circuit may comprise a direct current/direct current (DC/DC) converter configured to bypass a DC offset current of the resonance circuit. The first test valve may be an inverter unit, which may have a positive DC current offset. Further, the second test valve may be a rectifier unit, which may have a negative DC current offset.

Abstract: Provided is a synthetic test circuit for synthetic-testing a thyristor valve in high voltage direct current (HVDC). A resonant circuit applies forward DC current, a reverse DC voltage, and a forward DC voltage to synthetic-test the thyristor valve. A current generation unit generates DC current that is above a reference current value to supply the generated DC current into the resonant circuit. A voltage generates unit generating a DC voltage that is above a reference voltage value to supply the generated DC voltage into the resonant circuit. The resonant circuit includes a charging auxiliary valve for charging a gate driver of the thyristor valve.

Abstract: The present disclosure provides a method for controlling a multilevel converter, the method including, detecting modulation state values and current directions of sub-modules, and designating, by one sub-module, an average number of switching for each period of an output waveform, wherein the step of designating the average number of switching includes, grouping the sub-modules according to being in ON state or in OFF state, comparing the number of sub-modules in previous ON state and the number of sub-modules in OFF state to obtain a difference therebetween, and changing a state as much as the difference, comparing a sub-module of ON state in charged state and in discharged state with a sub-module of OFF state, and changing the compared states of sub-modules of ON state and OFF state.

Abstract: A power supply system includes: an electricity generation device configured to generate electrical energy; a plurality of DC/AC converters configured to convert the electrical energy into AC; and a battery energy storage system (BESS) configured to receive and charge the electrical energy and supplies the electrical energy to the plurality of DC/AC converters by discharging the charged electrical energy. The electrical energy generated by the electricity generation device charges the BESS without going through the plurality of DC/AC converters.

Abstract: Disclosed is a HVDC valve tower. The HVDC valve tower includes cylindrical valve module loading part, a valve module loaded on the valve module loading part, and a crane disposed at a center of the valve module loading part to be rotatable.

Abstract: An apparatus for testing a thyristor valve includes: a current source circuit that provides an electric current when a thyristor valve as a test target is turned on; a voltage source circuit that provides a reverse voltage or a forward voltage when the thyristor valve is turned off; and a first auxiliary valve provided between a connection point between the thyristor valve and the voltage source circuit and the current source circuit, and that insulates the current source circuit from the voltage source circuit to protect the current source circuit from a high voltage of the voltage source circuit.

Abstract: A method of controlling a multilevel converter is provided. In the method of controlling a multilevel converter according to an embodiment, a sub-module having the maximum voltage and a sub-module having the minimum voltage respectively are extracted from among a plurality of sub-modules. An amount of state variation of each of the plurality of sub-modules is determined. When the amount of state variation is not determined to be 0, a direction of a current flowing through the plurality of sub-modules is detected. A subsequent state of at least one sub-module is determined according to at least one of the amount of the state variation and current direction. Subsequently an arrangement time for sub-module values can be efficiently reduced while the number of the sub-modules increases in the voltage balancing.

Abstract: Provided is a synthetic test circuit for synthetic-testing a thyristor valve in high voltage direct current (HVDC). A resonant circuit applies forward DC current, a reverse DC voltage, and a forward DC voltage to synthetic-test the thyristor valve. A current generation unit generates DC current that is above a reference current value to supply the generated DC current into the resonant circuit. A voltage generates unit generating a DC voltage that is above a reference voltage value to supply the generated DC voltage into the resonant circuit. The resonant circuit includes a charging auxiliary valve for charging a gate driver of the thyristor valve.

Abstract: The present disclosure provides a method for controlling a multilevel converter, the method including, detecting modulation state values and current directions of sub-modules, and designating, by one sub-module, an average number of switching for each period of an output waveform, wherein the step of designating the average number of switching includes, grouping the sub-modules according to being in ON state or in OFF state, comparing the number of sub-modules in previous ON state and the number of sub-modules in OFF state to obtain a difference therebetween, and changing a state as much as the difference, comparing a sub-module of ON state in charged state and in discharged state with a sub-module of OFF state, and changing the compared states of sub-modules of ON state and OFF state.