Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

Abstract: A memory device includes a first memory block, a second memory block, a reception circuit configured to receiving a repair address and compression information, and a nonvolatile memory circuit including a first region for repairing the first memory block and a second region for repairing the second memory block, and configured to program the repair address in both the first region and the second region when the compression information represents high compression and program the repair address in either the first region or the second region when the compression information represents low compression.

Abstract: A redundancy control circuit includes: a fail address storage unit configured to store a fail address; a shared storage unit configured to store data as to whether a value stored in the fail address storage unit corresponds to both of a first address and a second address; an address comparator configured to compare a value stored in the fail address storage unit with a first input address and a second input address, respectively; and a redundancy controller configured to control a redundancy operation in response to a value stored in the shared storage unit and comparison results of the address comparator.

Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

Abstract: A semiconductor device includes: a plurality of fuse arrays each including a plurality of fuses; a selection block which selects one fuse array among the fuse arrays in response to values of a group of bits of a repair code; a code alignment block which aligns disposition of bits other than the group of bits of the repair code, wherein the alignment disposition is changed based on the fuse array selected in the selection block; and an operation block which controls an operation of the fuse array selected in the selection block in response to a repair command and an output code of the code alignment block.

Abstract: A memory device includes a first memory block, a second memory block, a reception circuit configured to receiving a repair address and compression information, and a nonvolatile memory circuit including a first region for repairing the first memory block and a second region for repairing the second memory block, and configured to program the repair address in both the first region and the second region when the compression information represents high compression and program the repair address in either the first region or the second region when the compression information represents low compression.

Abstract: A semiconductor device includes: a plurality of fuse arrays each including a plurality of fuses; a selection block which selects one fuse array among the fuse arrays in response to values of a group of bits of a repair code; a code alignment block which aligns disposition of bits other than the group of bits of the repair code, wherein the alignment disposition is changed based on the fuse array selected in the selection block; and an operation block which controls an operation of the fuse array selected in the selection block in response to a repair command and an output code of the code alignment block.

Abstract: A fuse repair device may include a first fuse circuit configured to store a first portion out of a failed address, a second fuse circuit configured to store a multipurpose information or a second portion of the failed address, an enable control circuit configured to provide a first enable signal to enable the second fuse unit based on a first control signal, a switch control circuit configured to provide a second enable signal to enable the second fuse unit based on a second control signal, a repair control signal generation circuit configured to compare data stored in the first fuse circuit and the second fuse circuit with an input address, and generate a repair control signal based on the first enable signal and the second enable signal, and a multipurpose control signal generation circuit configured to generate a multipurpose control signal to control operations different from a repair operation.

Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

Abstract: A fail address storage circuit includes a fail address storage unit configured to store a fail address and a discrimination information storage unit configured to store information indicating whether a value stored in the fail address storage unit is a row address or column address.

Abstract: A redundancy control circuit includes: a fail address storage unit configured to store a fail address; a shared storage unit configured to store data as to whether a value stored in the fail address storage unit corresponds to both of a first address and a second address; an address comparator configured to compare a value stored in the fail address storage unit with a first input address and a second input address, respectively; and a redundancy controller configured to control a redundancy operation in response to a value stored in the shared storage unit and comparison results of the address comparator.

Abstract: A fail address storage circuit includes a fail address storage unit configured to store a fail address and a discrimination information storage unit configured to store information indicating whether a value stored in the fail address storage unit is a row address or column address.

Abstract: A semiconductor memory device and a method for operating the same can improve a refresh characteristic of the semiconductor memory device by physically writing only logic low data in memory cells, irrespective of logic level of input data, either high or low. The semiconductor memory device includes a positive word line configured to control a first memory cell connected to a positive bit line, a negative word line configured to control a second memory cell connected to a negative bit line, and a word line control circuit configured to enable one of the positive word line and the negative word line according to a logic level of data in a write operation.

Abstract: The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path.

Abstract: A semiconductor memory device and a method for operating the same can improve a refresh characteristic of the semiconductor memory device by physically writing only logic low data in memory cells, irrespective of logic level of input data, either high or low. The semiconductor memory device includes a positive word line configured to control a first memory cell connected to a positive bit line, a negative word line configured to control a second memory cell connected to a negative bit line, and a word line control circuit configured to enable one of the positive word line and the negative word line according to a logic level of data in a write operation.

Abstract: The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path.

Abstract: A rapid response push-up pull-down buffer circuit configuration is used as an output buffer of a semiconductor memory device. The buffer circuit includes a pre-driver outputting a driving signal in response to an input data. The buffer circuit also includes an output driver driving an output signal in response to the driving signal which also has a driving strength adjusted in response to a level of the output signal. Accordingly, the driving strength can be automatically controlled in response to a level of the output signal which also results in enhancing the response speed of the buffer circuit.