Abstract: The present invention provides a novel prodrug of an edaravone compound or a pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising same as an active ingredient, and a use thereof in treatment or alleviation of neurodegenerative and/or motor neuron disease.

Abstract: The present invention relates to a UV-curable hydrogel resin for transdermal administration, a hydrogel prepared using the UV-curable hydrogel resin, and a cataplasm prepared using the UV-curable hydrogel resin. More particularly, the present invention relates to a hydrogel resin with an optimal composition and composition ratio which allows increase in a water content of a hydrogel applied as a drug layer of a cataplasm, skin irritation mitigation, and crosslinking degree adjustment for adhesion control and is capable of controlling drug releasing property and transdermal absorbability, a hydrogel prepared by UV-hardening the hydrogel resin, and a cataplasm including the hydrogel.

Abstract: The present invention provides a novel prodrug of an edaravone compound or a pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising same as an active ingredient, and a use thereof in treatment or alleviation of neurodegenerative and/or motor neuron disease.

Abstract: The present invention relates to a UV-curable hydrogel resin for transdermal administration, a hydrogel prepared using the UV-curable hydrogel resin, and a cataplasm prepared using the UV-curable hydrogel resin. More particularly, the present invention relates to a hydrogel resin with an optimal composition and composition ratio which allows increase in a water content of a hydrogel applied as a drug layer of a cataplasm, skin irritation mitigation, and crosslinking degree adjustment for adhesion control and is capable of controlling drug releasing property and transdermal absorbability, a hydrogel prepared by UV-hardening the hydrogel resin, and a cataplasm including the hydrogel.

Abstract: Provided are asymmetric arylamine derivatives for an organic electroluminescent element, represented by the formula (1), which is prepared by sequentially inducing a secondary amine and a tertiary amine to an aryl compound Ar core so that they do not include a symmetrical axis and a symmetrical surface in a molecule, a manufacturing method of the same, an organic thin layer material including the asymmetric arylamine derivatives, and an organic electroluminescent element employing the same: wherein Ar represents a C10-C20 divalent aryl group, Ar1 is a divalent C6-C30 aryl group, and Ar2 to Ar5 each independently represents a divalent C6-C30 aryl group, at least one of Ar2 to Ar5 having a different structure when the secondary amine and the tertiary amine in Ar are substituted at symmetrical positions, and Ar2 to Ar5 having the same structure or different structures when the secondary amine and the tertiary amine in Ar are substituted at asymmetrical positions.

Abstract: Provided are asymmetric arylamine derivatives for an organic electroluminescent element, represented by the formula (1), which is prepared by sequentially inducing a secondary amine and a tertiary amine to an aryl compound Ar core so that they do not include a symmetrical axis and a symmetrical surface in a molecule, a manufacturing method of the same, an organic thin layer material including the asymmetric arylamine derivatives, and an organic electroluminescent element employing the same: wherein Ar represents a C10-C20 divalent aryl group, Ar1 is a divalent C6-C30 aryl group, and Ar2 to Ar5 each independently represents a divalent C6-C30 aryl group, at least one of Ar2 to Ar5 having a different structure when the secondary amine and the tertiary amine in Ar are substituted at symmetrical positions, and Ar2 to Ar5 having the same structure or different structures when the secondary amine and the tertiary amine in Ar are substituted at asymmetrical positions.

Abstract: A MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, includes: gate insulating layers arranged at equal intervals in the form of a (n×m) matrix, and a gate electrode placed on the gate insulating layers in a well region of a substrate; a gate contact which contacts the gate electrode; a first metal wire, which is electrically connected to the gate contact; source/drain contacts arranged at equal intervals in a matrix to form apexes of a square centered at the gate electrode and contact a doping region except for the bottom of the gate insulating layers; and a second metal wire, which is electrically connected to the source/drain contacts.

Abstract: A nonvolatile semiconductor memory device and a method for manufacturing the same that may include forming an isolation pattern in a substrate, and then etching a portion of the isolation pattern to expose a portion of an active region of the substrate, and then forming high-density second-type ion implantation regions spaced apart at both edges of the active region by performing a tilted ion implantation process, and then forming a high-density first-type ion implantation region as a bit line in the active region, and then forming an insulating layer on the substrate including the high-density first-type ion implantation region, the high-density second-type ion implantation regions and the isolation pattern, and then forming a metal interconnection as a word line on the insulating layer pattern and extending in a direction perpendicular to bit line.

Abstract: The present invention provides a MOS varactor for use in circuits and elements of a millimeter-wave frequency band, which is capable of reducing series resistance and enhancing a Q-factor by using a plurality of island-like gates seated in a well region of a substrate and gate contacts directly over the gates, and a method of fabricating the MOS varactor.

Abstract: Provided is a method for manufacturing a semiconductor device. In the method, a gate oxide layer, a gate polysilicon layer, and a capping oxide layer are sequentially formed on a semiconductor substrate. A photoresist pattern is formed on the capping oxide layer. The capping oxide layer, gate polysilicon layer, and gate oxide layer are sequentially etched using the photoresist pattern as an etch mask. Ions are then implanted into the semiconductor substrate using the photoresist pattern as a mask. A thermal diffusion process is performed to form source/drain regions. The capping oxide layer is removed, and ions are implanted into the gate polysilicon layer. After metal is deposited on the gate polysilicon layer, a silicide is formed.

Abstract: Provided is a flash memory device and a method of manufacturing the same. In the method, a tunnel oxide layer pattern and a first polysilicon pattern are formed on a semiconductor substrate. A first dielectric layer including a first oxide layer, a first nitride layer, a second oxide layer, a second nitride layer and a third oxide layer is formed on the semiconductor substrate including the first polysilicon pattern. A second polysilicon pattern is formed on the dielectric layer pattern. The flash memory device includes a tunnel oxide layer pattern and a first polysilicon pattern on a semiconductor substrate; a dielectric layer on the first polysilicon pattern, including a first oxide layer pattern, a first nitride layer pattern, a second oxide layer pattern, a second nitride layer pattern and a third oxide layer pattern; and a second polysilicon pattern on the dielectric layer pattern.

Abstract: A nonvolatile semiconductor memory device and a method for manufacturing the same that may include forming an isolation pattern in a substrate, and then etching a portion of the isolation pattern to expose a portion of an active region of the substrate, and then forming high-density second-type ion implantation regions spaced apart at both edges of the active region by performing a tilted ion implantation process, and then forming a high-density first-type ion implantation region as a bit line in the active region, and then forming an insulating layer on the substrate including the high-density first-type ion implantation region, the high-density second-type ion implantation regions and the isolation pattern, and then forming a metal interconnection as a word line on the insulating layer pattern and extending in a direction perpendicular to bit line.

Abstract: A method of fabricating a semiconductor device may include forming a well in a semiconductor substrate, and then forming a gate oxide on and/or over the semiconductor substrate, and then forming a gate on and/or over the gate oxide, and then forming a pocket under the gate, and then performing a first spike anneal on the semiconductor substrate, and then performing a deep source/drain implant process on the semiconductor substrate, and then performing a second spike anneal on the semiconductor substrate.

Abstract: A method of forming a gate of a semiconductor device includes providing a semiconductor substrate in which an active region is defined by isolation films, forming a gate insulating film on the active region, forming a capping film on the gate insulating film, and performing an annealing process on the resulting surface and then forming a gate in part of the active region. The capping film is formed on the gate insulating film to prevent a reaction between the gate insulating film and subsequent gate materials, thereby preventing a phenomenon in which the work function of a gate changes and also the creation of a gate insulator having a low dielectric constant. The annealing process is performed under fluorine gas ambient to prevent trap sites within the gate insulating film while the gate can be composed of a metal or fully silicided gate to reduce the EOT.

Abstract: A method of fabricating a MOSFET device comprising forming a gate electrode pattern on a gate insulating layer on a semiconductor substrate, forming pre-source and pre-drain junction layers using a first ion implantation process on the substrate on each side of the gate electrode pattern, respectively, forming lightly doped drain junctions by performing a second ion implantation process on the surface of the pre-source and pre-drain junction layers, forming spacers on each side of the gate electrode pattern, and forming deep source and deep drain junction layers in the pre-source and pre-drain junction layers by performing third ion implantation process on the area of the substrate next to the gate electrode pattern.

Abstract: Embodiments relate to a semiconductor device and fabricating method thereof. In embodiments, a method of fabricating a semiconductor device may include forming a first gate insulating layer on a semiconductor substrate, performing first plasma nitridation on the first gate insulating layer, forming a second gate insulating layer on the first gate insulating layer, performing second plasma nitridation on the second gate insulating layer, forming a gate electrode metal material on the second gate insulating layer, and forming a metal gate electrode pattern by sequentially etching the gate electrode metal material, the second gate insulating layer, and the first gate insulating layer.

Abstract: Embodiments relate to a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating a MOSFET. According to embodiments, a method of forming a MOSFET may include forming a first gate insulating layer on a semiconductor substrate, nitrifying the first gate insulating layer, forming a second gate insulating layer on the first gate insulating layer, injecting fluorine ions into the second gate insulating layer, and diffusing the fluorine ions into the first gate insulating layer.

Abstract: A method for manufacturing a semiconductor device and the semiconductor device are provided. A mixed impurity of fluorine and boron are implanted into a polysilicon layer in a PMOS region. The fluorine and boron implanted polysilicon layer is etched to form a gate. The fluorine and boron reaction inhibits infiltration of the boron into a gate oxide film or gate spacer during a subsequent thermal process.

Abstract: A semiconductor device includes: a semiconductor substrate including source/drain regions and a channel between the source/drain regions; a gate oxide layer pattern on the channel; a metal nitride layer pattern on the gate oxide layer pattern; a silicide on the metal nitride layer pattern; and a spacer on a side of the gate oxide layer pattern, the metal nitride layer pattern, and the silicide. In one embodiment, the metal nitride layer pattern is ¼ to ½ as thick as the silicide.

Abstract: Provided is a method for manufacturing a semiconductor device. In the method, a gate oxide layer, a gate polysilicon layer, and a capping oxide layer are sequentially formed on a semiconductor substrate. A photoresist pattern is formed on the capping oxide layer. The capping oxide layer, gate polysilicon layer, and gate oxide layer are sequentially etched using the photoresist pattern as an etch mask. Ions are then implanted into the semiconductor substrate using the photoresist pattern as a mask. A thermal diffusion process is performed to form source/drain regions. The capping oxide layer is removed, and ions are implanted into the gate polysilicon layer. After metal is deposited on the gate polysilicon layer, a silicide is formed.