Abstract: The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.

Abstract: The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.

Abstract: The present disclosure generally relates to nanoparticles comprising a substantially hydrophobic acid, a basic therapeutic agent having a protonatable nitrogen, and a polymer. Other aspects include methods of making and using such nanoparticles.

Abstract: The present disclosure generally relates to nanoparticles comprising a substantially hydrophobic acid, a basic therapeutic agent having a protonatable nitrogen, and a polymer. Other aspects include methods of making and using such nanoparticles.

Abstract: Disclosed are a memory storing apparatus and method for preventing data loss after power loss. A memory storing method includes: determining a plurality of first user blocks scheduled to write data among a plurality of user blocks in which data is written, based on a recovery time of a mapping table required by a user; writing data in the determined first user blocks; writing a first mapping table in a spare area and a last page of the first user blocks in which the data is written; and switching the first user blocks written in the system page into second user blocks in which the data is completely written when data is written in all the first user blocks and writing a second mapping table for the switched second user blocks in a map page of a map block.

Abstract: A semiconductor apparatus may include: a buffer configured to store write request data input in response to a write request from a host; a memory device configured to store data evicted from the buffer; and a controller configured to control the buffer and the memory device to process the write request.

Abstract: A semiconductor apparatus may include: a buffer configured to store write request data input in response to a write request from a host; a memory device configured to store data evicted from the buffer; and a controller configured to control the buffer and the memory device to process the write request.

Abstract: An apparatus and method for changing an operation status of an electronic device using an embedded battery is provided. The apparatus and method for changing the operation status of the electronic device may detect an event that requires a change in the operation status of the electronic device, may switch a battery used for an operation of the electronic device from a first battery detachable from the electronic device to a second battery embedded in the electronic device, in response to detecting the event, and may change the operation status of the electronic device by employing the second battery as a power source.

Abstract: An apparatus and method for managing flash memory based on recognition of patterns of write-target data are disclosed. A data analysis unit analyzes bit storage patterns that are stored in cells of the flash memory, and a data matching unit matches corresponding alternative patterns to the bit storage patterns based on the results of the analysis of the data analysis unit. According to the present invention, the reliability and durability of NAND flash memory can be improved because a minimum number of “0” bits are stored in a page. Furthermore, the application of the technology is easy and simple because a memory controller can perform management without changes in the structure and cell arrangement of a NAND flash device.

Abstract: Provided are an interface system and a method of controlling the interface system. The interface system may include a memory, a first processor, a second processor, and an interface unit. The memory may be configured to store received data in packets. The first processor may be configured to analyze a header of each of the packets to obtain analysis information. The second processor may be configured to receive and process a payload of the packet that includes the analyzed header and the payload. The interface unit may be configured to transmit only the payload to the second processor based on the analysis information. Since the interface system and the method may directly transmit only the payload of the packet to the processor without copying the payload to a separate memory, memory usage efficiency and system performance may be improved and power consumption may be reduced.

Abstract: An apparatus and method for packet routing in a high-speed packet routing system. The apparatus includes an input unit and a control unit. The input unit temporarily stores an input packet and outputs the temporarily stored input packet to an output port determined by a previous router. The control unit determines an output port of a next router for the input packet.

Abstract: Provided are an interface system and a method of controlling the interface system. The interface system may include a memory, a first processor, a second processor, and an interface unit. The memory may be configured to store received data in packets. The first processor may be configured to analyze a header of each of the packets to obtain analysis information. The second processor may be configured to receive and process a payload of the packet that includes the analyzed header and the payload. The interface unit may be configured to transmit only the payload to the second processor based on the analysis information. Since the interface system and the method may directly transmit only the payload of the packet to the processor without copying the payload to a separate memory, memory usage efficiency and system performance may be improved and power consumption may be reduced.

Abstract: A bus analyzer used in a multiprocessor computer system having a common system bus includes a bus tester for storing test data used to test the system bus and internal data paths of the bus analyzer. The test data is output to the system bus to initiate a testing operation. A trace memory sequentially receives and stores the test data provided from the system bus. A memory controller controls the trace memory to store the test data received from the system bus in response to a trace signal and interrupt storage of the test data in response to a trigger signal. A test controller generates the trace signal and the trigger signal output to the memory controller, reads the test data stored in the trace memory, and compares the test data read from the trace memory with the test data stored in the bus tester. The bus analyzer of the present invention is capable of independently testing its own internal data paths without signals provided from an external source or additional apparatus.