Patents by Inventor Yong Hou

Yong Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140194300
    Abstract: Provided are the method and device for genetic map construction and the method and device for haplotype determination of a single cell.
    Type: Application
    Filed: August 24, 2012
    Publication date: July 10, 2014
    Applicant: BGI Tech Solutions Co., Ltd.
    Inventors: Luting Song, Di Shao, Zequn Zheng, Zhijun Zheng, Kui Wu, Shuheng Liang, Ye Tao, Yong Hou
  • Patent number: 7148089
    Abstract: An improved fuse link structure and method of forming the same, the method including forming a dual damascene structure by a trench-first process to form a dual damascene having a relatively thinner fuse link portion spanning an area between and overlying fuse metal interconnect structures including a mechanically robust dielectric insulating layer portion underlying the relatively thinner fuse link portion.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: December 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Chi Hung, Hao-Yi Tsai, Shang-Yong Hou
  • Publication number: 20050056827
    Abstract: Three configurations of double barrier resonant tunneling diodes (RTD) are provided along with methods of their fabrication. The tunneling barrier layers of the diode are formed of low band offset dielectric materials and produce a diode with good I-V characteristics including negative differential resistance (NDR) with good peak-to-valley ratios (PVR). Fabrication methods of the RTD start with silicon-on-insulator substrates (SOI), producing silicon quantum wells, and are, therefore, compatible with main stream CMOS technologies such as those applied to SOI double gate transistor fabrication. Alternatively, Ge-on-insulator or SiGe-on-insulator substrates can be used if the quantum well is to be formed of Ge or SiGe. The fabrication methods include the formation of both vertical and horizontal silicon quantum well layers. The vertically formed layer may be oriented so that its vertical sides are in any preferred crystallographic plane, such as the 100 or 110 planes.
    Type: Application
    Filed: January 29, 2004
    Publication date: March 17, 2005
    Inventors: Ming Li, Jagar Singh, Yong Hou, Narayanan Balasubramanian, Fujiang Lin