Patents by Inventor YONG-HUN AHN

YONG-HUN AHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240076127
    Abstract: Provided is a ceiling storage system capable of correcting a working position and constantly checking stability of a structure by detecting an amount of change in a facility. According to the ceiling storage system, a transport vehicle moves to an upper portion of a first storage area of a plurality of storage areas in a state of gripping an article, and the transport vehicle measures a first distance value between the transport vehicle and the first storage area using a distance sensor and measures a relative position value between the transport vehicle and the first storage area using a vision sensor, before unloading the article from the first storage area.
    Type: Application
    Filed: May 23, 2023
    Publication date: March 7, 2024
    Inventors: Sang Kyung LEE, Seung Gyu KANG, Hyun Jae KANG, Young Wook KIM, Sang A BANG, Yong-Jun AHN, Min Kyun LEE, Hyun Woo LEE, Jeong Hun LIM, Jun Hyuk CHANG
  • Patent number: 8928349
    Abstract: An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seok Oh, Joon-Young Park, Yong-Hun Ahn, Yong-Cheol Bae, Yong-Gwon Jeong, Jong-Hyun Choi
  • Publication number: 20140028345
    Abstract: An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.
    Type: Application
    Filed: January 31, 2013
    Publication date: January 30, 2014
    Inventors: KI-SEOK OH, JOON-YOUNG PARK, YONG-HUN AHN, YONG-CHEOL BAE, YONG-GWON JEONG, JONG-HYUN CHOI