Abstract: In the water filter assembly, the flow path could be changed to the bypass flow path or the purified water flow path, when the inner moves upwardly and downwardly in the filter head by combining or separating of the filter body and filter head. The inner is movably inserted to the filter head. The elastic member changes the flow path to bypass flow path when the filter body is separated by elastic biasing the inner between the filter head and the inner to downward direction of the filter head. If the user pushes the inner to the inside of the filter head by mistake when the filter body is separated from the filter head, the inner is pushed out to be the original position, so that the filter body can be rapidly combined to the filter head including the inner.

Abstract: In the water filter assembly, the flow path could be changed to the bypass flow path or the purified water flow path, when the inner moves upwardly and downwardly in the filter head by combining or separating of the filter body and filter head. The inner is movably inserted to the filter head. The elastic member changes the flow path to bypass flow path when the filter body is separated by elastic biasing the inner between the filter head and the inner to downward direction of the filter head. If the user pushes the inner to the inside of the filter head by mistake when the filter body is separated from the filter head, the inner is pushed out to be the original position, so that the filter body can be rapidly combined to the filter head including the inner.

Abstract: To measure an inner temperature of a chamber included in a test handler, self-refresh currents of semiconductor memory devices under test are measured. The semiconductor memory devices are disposed in the chamber and have a function of linear temperature compensated self-refresh (Li-TCSR). Local temperature values are generated based on the self-refresh currents, where each local temperature value indicates a temperature near the corresponding semiconductor memory device of the semiconductor memory devices under test.

Abstract: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

Abstract: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

Abstract: A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Abstract: Disclosed is a peripheral device integrated ubiquitous multifunction PC in which an internet phone device and a PLC modem are integrated. The multifunction PC integrated with a monitor includes a main body including a case provided with basic components and an internet telephone apparatus, and an LCD panel at the front side, and a stand at the lower side of the main body to support the main body. The main body includes a power supply of the case and connected to a power line, a modem provided in the case and including a PLC modem connected to the power supply to modulate/demodulate a signal transmitted through the power line, a telephone receiver provided at a side of the case, and a web-camera provided at the front upper side of the case. The stand includes dial buttons and a key telephone that are provided in the front side thereof.

Abstract: An apparatus for automatically analyzing various solutions which are used in the production lines of various industrial fields. Particularly, in the case where the ingredients of a solution is to be analyzed, the test sample is taken in an automatic manner, and carried over a long distance. The carried test sample is subjected to an automatic pre-treatment and an automatic ingredient analysis. Thus the ingredients of a solution can be analyzed in a speedy and accurate manner. Further, the results of the analysis are treated with an on-line real time to be fed back in a speedy manner, and therefore, it is made possible to strictly control the solution ingredients, thereby contributing to the improvement of the quality of products. Furthermore, the expensive analyzing instruments can be protected from corrosion.