Abstract: In the case of a gas in which several gases are mixed, a type and concentration of the gas may be incorrectly measured when measured using only an optical band-pass filter. The invention of the present application is directed to providing a technology in which a plurality of broadband band-pass filters having overlapping regions are provided to calculate a magnitude of absorption for each wavelength band for light passing through each broadband band-pass filter, thereby identifying the presence of a gas of interest and the presence of a gas other than the gas of interest.

Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.

Abstract: A smart sling device includes a body; a support rod installed at the body; and a sling member installed at the support rod and inserted under a patient to support the patient therebelow, and the sling member includes an expanding unit having an accommodation space for accommodating air therein, the expanding unit expanding due to a pneumatic pressure generated by the accommodated air to support the patient therebelow; and an expansion limiting unit installed at the expanding unit to limit expansion of the expanding unit in one direction.

Abstract: A data transmission circuit which is improved to be capable of supporting a data transmission mode appropriate for an interface or an application depending on the selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential driving signal, a second differential driving signal and pre-emphasis control signals by using a first differential data signal, a second differential data signal and option signals; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential driving signal and the second differential driving signal; and a pre-emphasis driver configured to perform pre-emphasis on the first differential transmission signal and the second differential transmission signal to different amplification degrees in a first mode and a second mode by the pre-emphasis control signals.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which enable the influence of high voltage noise to be avoided in display panel driving. The display device includes a timing controller configured to transmit a communication signal, which includes a blank pattern and line data, at a horizontal line interval, and a source driver configured to restore the blank pattern and the line data in the communication signal and drive a display panel using the blank pattern and the line data. The timing controller may include a configuration packet in the blank pattern and position the configuration packet in an end period of the blank pattern.

Abstract: Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which allow transmission data to be converted into a completely random code sequence. The display device may scramble transmission data into a pseudo-random binary sequence (PRBS) using a linear feedback shift register (LFSR), and may change a seed value of the LFSR every time the scrambling is performed.

Abstract: The present disclosure discloses a display driving device and a display device including the same, allowing high-speed data communication to be supported by controlling the length of a data packet. The display device may include a timing controller configured to transmit a communication signal, and a source driver connected to the timing controller through a communication link and configured to receive the communication signal. The source driver may receive the communication signal having a format of preamble data, start data, configuration data, end data, and configuration completion data from the timing controller in a configuration mode, and the configuration data may include a header defining a length of a data packet.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which are capable of restoring a communication abnormal state to a normal state when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a plurality of source drivers. The display device may include a timing controller configured to transmit a communication signal, a first source driver connected to the timing controller through a first communication link and configured to receive the communication signal, and a second source driver connected to the timing controller through a second communication link and configured to receive the communication signal.

Abstract: A smart sling device includes a body; a support rod installed at the body; and a sling member installed at the support rod and inserted under a patient to support the patient therebelow, and the sling member includes an expanding unit having an accommodation space for accommodating air therein, the expanding unit expanding due to a pneumatic pressure generated by the accommodated air to support the patient therebelow; and an expansion limiting unit installed at the expanding unit to limit expansion of the expanding unit in one direction.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which are capable of restoring a communication abnormal state to a normal state when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a plurality of source drivers. The display device may include a timing controller configured to transmit a communication signal, a first source driver connected to the timing controller through a first communication link and configured to receive the communication signal, and a second source driver connected to the timing controller through a second communication link and configured to receive the communication signal.

Abstract: The present disclosure discloses a display driving device and a display device including the same, allowing high-speed data communication to be supported by controlling the length of a data packet. The display device may include a timing controller configured to transmit a communication signal, and a source driver connected to the timing controller through a communication link and configured to receive the communication signal. The source driver may receive the communication signal having a format of preamble data, start data, configuration data, end data, and configuration completion data from the timing controller in a configuration mode, and the configuration data may include a header defining a length of a data packet.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which allow transmission data to be converted into a completely random code sequence. The display device may scramble transmission data into a pseudo-random binary sequence (PRBS) using a linear feedback shift register (LFSR), and may change a seed value of the LFSR every time the scrambling is performed.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which enable the influence of high voltage noise to be avoided in display panel driving. The display device includes a timing controller configured to transmit a communication signal, which includes a blank pattern and line data, at a horizontal line interval, and a source driver configured to restore the blank pattern and the line data in the communication signal and drive a display panel using the blank pattern and the line data. The timing controller may include a configuration packet in the blank pattern and position the configuration packet in an end period of the blank pattern.

Abstract: Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

Abstract: A data transmission circuit which is improved to be capable of supporting a data transmission mode appropriate for an interface or an application depending on the selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential driving signal, a second differential driving signal and pre-emphasis control signals by using a first differential data signal, a second differential data signal and option signals; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential driving signal and the second differential driving signal; and a pre-emphasis driver configured to perform pre-emphasis on the first differential transmission signal and the second differential transmission signal to different amplification degrees in a first mode and a second mode by the pre-emphasis control signals.

Abstract: Disclosed is a clock recovery system of a display apparatus including a clock recovery unit which uses changeable option information used for recovering a clock signal and defining a duty, generates delayed clock signals having the duty corresponding to the option information in a clock training section, and outputs one of the delayed clock signals as the clock signal.

Abstract: Disclosed is a clock recovery system of a display apparatus including a clock recovery unit which uses changeable option information used for recovering a clock signal and defining a duty, generates delayed clock signals having the duty corresponding to the option information in a clock training section, and outputs one of the delayed clock signals as the clock signal.

Abstract: Provided are an embedded DisplayPort (eDP) system and a method for controlling a panel self refresh mode. The eDP system enters a panel self refresh (PSR) mode when an image to display is static in a general mode, and a sink device recovers a stream clock for displaying a static image in the PSR mode.

Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.