Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.

Abstract: An assembly for pushing an electrode into a glass melting vessel can include a frame, a shaft, a pusher actuator, a contact mechanism, a master actuator, and a torque limiter. The contact mechanism can be attached to the shaft. The pusher actuator can be mounted to the frame and configured to cause translation of the shaft and the contact mechanism relative to the frame. The master actuator can be operatively connected to the pusher actuator such that operation of the master actuator causes operation of the pusher actuator. The torque limiter can be operatively connected between the master actuator and the pusher actuator, and can be configured to disengage when a rotational force on the master actuator exceeds a predetermined amount.

Abstract: According to some embodiments, a gate electrode structure including a gate electrode stack and a spacer, and source/drain region are formed on a semiconductor substrate. A first interlayer insulating layer having a thickness greater than that of the gate electrode structure is formed on the semiconductor substrate. On the first interlayer insulating layer, an etch inducing and focusing mask extending in a same direction as a length direction of the gate electrode structure and covering the gate electrode structure is formed. A second interlayer insulating layer is formed on the first interlayer insulating layer. A photoresist pattern is formed on the second interlayer insulating layer. The second interlayer insulating layer and the first interlayer insulating layer are sequentially etched using the photoresist pattern as an etch mask, thereby forming a SAC hole. A conductive material is used to fill in the SAC hole to form a SAC pad.

Abstract: According to some embodiments, a gate electrode structure including a gate electrode stack and a spacer, and source/drain region are formed on a semiconductor substrate. A first interlayer insulating layer having a thickness greater than that of the gate electrode structure is formed on the semiconductor substrate. On the first interlayer insulating layer, an etch inducing and focusing mask extending in a same direction as a length direction of the gate electrode structure and covering the gate electrode structure is formed. A second interlayer insulating layer is formed on the first interlayer insulating layer. A photoresist pattern is formed on the second interlayer insulating layer. The second interlayer insulating layer and the first interlayer insulating layer are sequentially etched using the photoresist pattern as an etch mask, thereby forming a SAC hole. A conductive material is used to fill in the SAC hole to form a SAC pad.

Abstract: A method is disclosed for manufacturing a semiconductor device. Initially, a conductive layer is formed over a cell array region, in which high-integrated devices are formed, and over a non-cell region, which functions to assist a proper formation of the cell array region. An etching mask pattern is then formed over the conductive layer to form a conductive pattern over the cell array region and to remove the conductive layer formed on the non-cell region. The conductive pattern is actually formed by etching the conductive layer. An ion-assisted plasma etching is then implemented to form a pattern on the cell array region. This prevents the generation of arcing caused by independent conductive patterns formed on the non-cell region during the ion-assisted plasma etching.