Abstract: A display driving circuit having a lock function includes a comparison unit configured to receive a transfer lock signal and output a comparison signal obtained by comparing the transfer lock signal and an internal lock signal obtained by determining a state of an internal recovery clock; and an output circuit comprising an internal output pull-up circuit and configured to generate a feedback lock signal having a level corresponding to a level of the comparison signal by using the internal output pull-up circuit and to output the feedback lock signal to a lock signal transmission line to which an external power source is applied.

Abstract: The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

Abstract: The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

Abstract: The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

Abstract: The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

Abstract: Disclosed is a clock recovery system of a display apparatus including a clock recovery unit which uses changeable option information used for recovering a clock signal and defining a duty, generates delayed clock signals having the duty corresponding to the option information in a clock training section, and outputs one of the delayed clock signals as the clock signal.

Abstract: The present invention relates to a display apparatus which drives a display panel to display an image, and a driving circuit thereof. The display apparatus includes a timing controller configured to provide a control option having a value for compensating for pixel data and a gray scale, and a driving circuit configured to combines the control option and the pixel data and output an output voltage.

Abstract: Disclosed is a clock recovery system of a display apparatus including a clock recovery unit which uses changeable option information used for recovering a clock signal and defining a duty, generates delayed clock signals having the duty corresponding to the option information in a clock training section, and outputs one of the delayed clock signals as the clock signal.

Abstract: A source driver may include: a transmission line configured to transmit an output signal of a sample and hold circuit which stores pixel information of an organic light emitting diode (OLED) cell; an amplifier is formed a first offset voltage at an input terminal by a parasitic capacitor of the transmission line; and an offset voltage storage unit configured to store the first offset voltage outputted from the amplifier as a second offset voltage while the transmission of the output signal of the sample and hold circuit through the transmission line is turned off, and offset the first offset voltage by providing the second offset voltage to the input terminal of the amplifier when the output signal of the sample and hold circuit is transmitted through the transmission line.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: The present invention relates to a display apparatus which drives a display panel to display an image, and a driving circuit thereof. The display apparatus includes a timing controller configured to provide a control option having a value for compensating for pixel data and a gray scale, and a driving circuit configured to combines the control option and the pixel data and output an output voltage.

Abstract: A sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

Abstract: A display driving circuit may include: an output buffer unit including a plurality of output buffer pairs, wherein among the plurality of output buffer pairs, each of first output buffers has a first voltage driving potential, and each of second output buffers has a second voltage driving potential; an output switch unit configured to directly connect the plurality of output buffer pairs to a plurality of output line pairs or cross and connect the plurality of output buffer pairs to the plurality of output line pairs; and a charge sharing switch unit configured to connect first output lines corresponding to the first output buffers, and connect second output lines corresponding to the second output buffers. Through this configuration, the display driving circuit can reduce power consumption and heat generation.

Abstract: A source driver may include: a transmission line configured to transmit an output signal of a sample and hold circuit which stores pixel information of an organic light emitting diode (OLED) cell; an amplifier is formed a first offset voltage at an input terminal by a parasitic capacitor of the transmission line; and an offset voltage storage unit configured to store the first offset voltage outputted from the amplifier as a second offset voltage while the transmission of the output signal of the sample and hold circuit through the transmission line is turned off, and offset the first offset voltage by providing the second offset voltage to the input terminal of the amplifier when the output signal of the sample and hold circuit is transmitted through the transmission line.

Abstract: A sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.