Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A capacitor of a semiconductor device and a distributed model circuit for the same are disclosed. The capacitor includes a lower electrode layer, a plurality of upper electrode layers disposed over the lower electrode layer, a plurality of dielectric layers disposed between the lower electrode layer and each of the plurality of upper electrode layers, each dielectric layer configured to include a plurality of storage nodes, a plurality of line layers disposed over at least one of the plurality of upper electrode layers, and configured to receive a voltage for measuring an equivalent series resistance (ESR), and a plurality of contacts that electrically couple the plurality of line layers to the at least one of the plurality of upper electrode layers, wherein a resistance resulting from position information of the plurality of line layers and the plurality of contacts in a routing pattern corresponds to the ESR.

Abstract: A display device may include a substrate, an organic light emitting layer overlapping the substrate and including an opening, and a holed insulating layer positioned between the substrate and the organic light emitting layer. The holed insulating layer may include a first through hole, a first groove, and a first undercut. A position of the opening may overlap a position of the first groove. The first groove may surround the first through hole in a plan view of the display device. The first undercut may surround the first groove in the plan view of the display device.

Abstract: A capacitor of a semiconductor device and a distributed model circuit for the same are disclosed. The capacitor includes a lower electrode layer, a plurality of upper electrode layers disposed over the lower electrode layer, a plurality of dielectric layers disposed between the lower electrode layer and each of the plurality of upper electrode layers, each dielectric layer configured to include a plurality of storage nodes, a plurality of line layers disposed over at least one of the plurality of upper electrode layers, and configured to receive a voltage for measuring an equivalent series resistance (ESR), and a plurality of contacts that electrically couple the plurality of line layers to the at least one of the plurality of upper electrode layers, wherein a resistance resulting from position information of the plurality of line layers and the plurality of contacts in a routing pattern corresponds to the ESR.

Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A display device includes: a substrate comprising a first layer and a second layer; a first display area including a first pixel area on the substrate; a second display area including a second pixel area and a transparent area adjacent to each other on the substrate; and a blocking layer disposed in the second pixel area of the second display area, and disposed between a first layer and a second layer of the substrate in a side view, and the blocking layer including a metal blocks light.

Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A display device may include a substrate, an organic light emitting layer overlapping the substrate and including an opening, and a holed insulating layer positioned between the substrate and the organic light emitting layer. The holed insulating layer may include a first through hole, a first groove, and a first undercut. A position of the opening may overlap a position of the first groove. The first groove may surround the first through hole in a plan view of the display device. The first undercut may surround the first groove in the plan view of the display device.

Abstract: An electronic device includes: a display panel including a display region including a first display region and a second display region having a higher transmittance than the first display region and an electronic module below the second display region of the display panel, wherein the display panel includes: a base layer; a plurality of first pixel electrodes on the base layer and in the first display region; a plurality of second pixel electrodes on the base layer and in the second display region; a common electrode on the plurality of first pixel electrodes and the plurality of second pixel electrodes and in which a plurality of openings are defined; and a blocking pattern spaced apart from the common electrode with the plurality of second pixel electrodes interposed therebetween and having a plurality of transmission portions overlapping the plurality of openings.

Abstract: A capacitor of a semiconductor device and a distributed model circuit for the same are disclosed. The capacitor includes a lower electrode layer, a plurality of upper electrode layers disposed over the lower electrode layer, a plurality of dielectric layers disposed between the lower electrode layer and each of the plurality of upper electrode layers, each dielectric layer configured to include a plurality of storage nodes, a plurality of line layers disposed over at least one of the plurality of upper electrode layers, and configured to receive a voltage for measuring an equivalent series resistance (ESR), and a plurality of contacts that electrically couple the plurality of line layers to the at least one of the plurality of upper electrode layers, wherein a resistance resulting from position information of the plurality of line layers and the plurality of contacts in a routing pattern corresponds to the ESR.

Abstract: A display device may include a substrate, an organic light emitting layer overlapping the substrate and including an opening, and a holed insulating layer positioned between the substrate and the organic light emitting layer. The holed insulating layer may include a first through hole, a first groove, and a first undercut. A position of the opening may overlap a position of the first groove. The first groove may surround the first through hole in a plan view of the display device. The first undercut may surround the first groove in the plan view of the display device.

Abstract: A display device includes: a substrate comprising a first layer and a second layer; a first display area including a first pixel area on the substrate; a second display area including a second pixel area and a transparent area adjacent to each other on the substrate; and a blocking layer disposed in the second pixel area of the second display area, and disposed between a first layer and a second layer of the substrate in a side view, and the blocking layer including a metal blocks light.

Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.

Abstract: A display device may include a substrate, an organic light emitting layer overlapping the substrate and including an opening, and a holed insulating layer positioned between the substrate and the organic light emitting layer. The holed insulating layer may include a first through hole, a first groove, and a first undercut. A position of the opening may overlap a position of the first groove. The first groove may surround the first through hole in a plan view of the display device. The first undercut may surround the first groove in the plan view of the display device.

Abstract: A display apparatus includes a first substrate, a second substrate, and a driver chip. The first substrate includes a plurality of gate lines disposed in the display area and extended in a first direction, a plurality of data lines disposed on a gate insulating layer insulating the gate lines and extended in a second direction substantially perpendicular to the first direction, and a gate driving circuit section disposed in the first peripheral area adjacent to first ends of the gate lines. The second substrate is opposite to the first substrate. A liquid crystal is interposed between the first and second substrates. The driver chip is disposed in the second peripheral area adjacent to second ends of the gate lines opposite to the first ends so that the width of the upper and lower portions of the display area may be decreased.

Abstract: A display substrate includes a display area corresponding to a plurality of pixels, a peripheral area surrounding the display area, a thin film transistor for driving a corresponding one of the pixels, a gate line electrically coupled to the thin film transistor, a data line crossing the gate line and electrically coupled to the thin film transistor, a pixel electrode electrically coupled to the thin film transistor, and a common electrode overlapping the pixel electrode and having a first opening overlapping a first pixel of the pixels, and a second opening overlapping a second pixel of the pixels adjacent the first pixel, wherein the first opening and the second opening extend in different directions, and wherein the common electrode is continuous and overlaps the first and second pixels.

Abstract: A display apparatus includes a first substrate, a second substrate, and a driver chip. The first substrate includes a plurality of gate lines disposed in the display area and extended in a first direction, a plurality of data lines disposed on a gate insulating layer insulating the gate lines and extended in a second direction substantially perpendicular to the first direction, and a gate driving circuit section disposed in the first peripheral area adjacent to first ends of the gate lines. The second substrate is opposite to the first substrate. A liquid crystal is interposed between the first and second substrates. The driver chip is disposed in the second peripheral area adjacent to second ends of the gate lines opposite to the first ends so that the width of the upper and lower portions of the display area may be decreased.

Abstract: A display apparatus includes a first substrate, a second substrate, and a driver chip. The first substrate includes a plurality of gate lines disposed in the display area and extended in a first direction, a plurality of data lines disposed on a gate insulating layer insulating the gate lines and extended in a second direction substantially perpendicular to the first direction, and a gate driving circuit section disposed in the first peripheral area adjacent to first ends of the gate lines. The second substrate is opposite to the first substrate. A liquid crystal is interposed between the first and second substrates. The driver chip is disposed in the second peripheral area adjacent to second ends of the gate lines opposite to the first ends so that the width of the upper and lower portions of the display area may be decreased.