Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Abstract: Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion.

Abstract: Provided are a wire bonding apparatus and a method wire bonding and manufacturing a semiconductor device using the same. The wire bonding apparatus includes a heater block configured to support a stack including a chip mounting frame and a plurality of chips stacked on the chip mounting frame. The heater block is configured to supply heat to a first portion of the stack. The apparatus further includes a chip heating unit disposed at a different height from the heater block. The chip heating unit is configured to supply heat to a second portion of the stack at a different height from the first portion.

Abstract: A multi-chip package may include a package substrate, a plurality of semiconductor chips and conductive connecting members. The semiconductor chips may be sequentially stacked on the package substrate. Each of the semiconductor chips may include a signal pad and a test pad. The conductive wires may be electrically connected between the signal pad of an upper semiconductor chip among the semiconductor chips and the package substrate via the test pad of a lower semiconductor chip under the upper semiconductor chip. The test pad may be converted into the dummy pad by cutting a fuse.