Abstract: Provided is a vehicle control apparatus including an image obtaining part that obtains an image of outside of a vehicle; a face recognizing part that finds and tracks a face of a person from an image obtained by the image obtaining part based on feature elements human faces and extracts feature information regarding a face of a person; a face authenticating part that compares the feature information extracted by the face recognizing part to feature information regarding faces of persons registered in advance and, if a difference therebetween is less than or equal to a critical value, authenticates that the recognized face as a registered face; the motion recognizing part that, when authentication is completed by the face authenticating part, recognizes a motion; and a control part that recognizes a motion of a face-recognized and face-authenticated person and performs a set function.

Abstract: Provided is a vehicle control apparatus including an image obtaining part that obtains an image of outside of a vehicle; a face recognizing part that finds and tracks a face of a person from an image obtained by the image obtaining part based on feature elements human faces and extracts feature information regarding a face of a person; a face authenticating part that compares the feature information extracted by the face recognizing part to feature information regarding faces of persons registered in advance and, if a difference therebetween is less than or equal to a critical value, authenticates that the recognized face as a registered face; the motion recognizing part that, when authentication is completed by the face authenticating part, recognizes a motion; and a control part that recognizes a motion of a face-recognized and face-authenticated person and performs a set function.

Abstract: Provided are an orthogonal frequency division multiple assess (OFDMA) system and a method for controlling frequency offsets of subscribers in uplink communication. The OFDMA system solves a problem that the system performance is deteriorated in uplink communications because subscriber stations have different carrier frequency offsets. Each subscriber station compensates for a frequency offset thereof in response to a frequency offset control signal provided by a base station and then transmits an uplink frame to the base station. The base station compensates for an average frequency offset using the uplink frame, which has a small frequency offset shift because each subscriber station compensates for the frequency offset thereof previously, and thus the frequency offset of each subscriber station can be correctly compensated to prevent inter-carrier interference.

Abstract: Provided are an orthogonal frequency division multiple assess (OFDMA) system and a method for controlling frequency offsets of subscribers in uplink communication. The OFDMA system solves a problem that the system performance is deteriorated in uplink communications because subscriber stations have different carrier frequency offsets. Each subscriber station compensates for a frequency offset thereof in response to a frequency offset control signal provided by a base station and then transmits an uplink frame to the base station. The base station compensates for an average frequency offset using the uplink frame, which has a small frequency offset shift because each subscriber station compensates for the frequency offset thereof previously, and thus the frequency offset of each subscriber station can be correctly compensated to prevent inter-carrier interference.

Abstract: The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.

Abstract: A method and apparatus for defining, in a computing system, the bit size of an instruction to be executed by a processing unit. Instructions are realized in the form of a plurality of memory location devices. At least one of said memory location devices, in a predetermined position, is established as a MODE bit. The MODE bit assumes a first value indicative of parallel instruction execution and assumes a second value indicative of non-parallel instruction execution.