Patents by Inventor Yong Jiang

Yong Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060290396
    Abstract: A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 28, 2006
    Inventor: Yong Jiang
  • Patent number: 7134010
    Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: November 7, 2006
    Assignee: Broadcom Corporation
    Inventors: Jonathan Lin, Yong Jiang
  • Patent number: 7093384
    Abstract: An iron comprising a housing (1), a heatable soleplate (4) and means for generating very fine liquid droplets to be expelled from at least one discharge opening (9) of the iron, said means comprising at least one air passage (8) for pressurized air supply and at least one liquid passage (13) for pressurized liquid supply, said air passage (8) and said liquid passage (13) communicating with each other for mixing air and liquid, said mixture of air and liquid being supplied to the discharge opening (9). To improve the generation of fine liquid droplets (mist) an outlet of the liquid passage (8) ends into the air passage (13) upstream of the discharge opening (9) to introduce liquid into the air passage and an outlet of the air passage is provided with a nozzle (10) having said discharge opening (9). Preferably the pressurized air and liquid supply is obtained by means of electric pumps (6,7). The liquid may be water or a (diluted) additive liquid.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: August 22, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Nyik Siong Wong, Yong Jiang, Tao Guo, Kumar Asok SO Kasevan
  • Patent number: 7024576
    Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: April 4, 2006
    Assignee: Broadcom Corporation
    Inventors: Jonathan Lin, Yong Jiang
  • Publication number: 20050278987
    Abstract: An electric iron having a housing (1) and a soleplate (2) in which at least one outlet opening (10;15;34;45) is provided, means (8;19;28;39;43) for generating a fine liquid spray or foam or steam, and means (5) for delivering said generated fine liquid spray or foam or steam through said outlet opening. According to the invention, the iron is provided with detection means (12,14;22,23;35,36;49) for detecting the presence of a surface (7a) in the proximity of the sloplate (2) and for generating a detection signal in response to said detection, and with control means (6) for controlling the delivery of said fine liquid spray or foam or steam in response of said detection signal. For example, the detection means comprise a movable spring-loaded contact element (12) located in the soleplate (2), said element (12) activating a switch (14) for generating said signal when the soleplate is positioned against said surface (7a) and thus depresses said element (12).
    Type: Application
    Filed: July 1, 2003
    Publication date: December 22, 2005
    Inventors: Boon Ching, Yong Jiang, Nyik Wong, Tang Har
  • Publication number: 20050268138
    Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.
    Type: Application
    Filed: July 14, 2005
    Publication date: December 1, 2005
    Inventors: Jonathan Lin, Yong Jiang
  • Publication number: 20050268140
    Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 1, 2005
    Inventors: Jonathan Lin, Yong Jiang
  • Patent number: 6934866
    Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: August 23, 2005
    Assignee: Broadcom Corporaton
    Inventors: Jonathan Lin, Yong Jiang
  • Patent number: 6920552
    Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: July 19, 2005
    Assignee: Broadcom Corporation
    Inventors: Jonathan Lin, Yong Jiang
  • Publication number: 20050069302
    Abstract: An iron comprising a housing (1), a heatable soleplate (4) and means for generating very fine liquid droplets to be expelled from at least one discharge opening (9) of the iron, said means comprising at least one air passage (8) for pressurized air supply and at least one liquid passage (13) for pressurized liquid supply, said air passage (8) and said liquid passage (13) communicating with each other for mixing air and liquid, said mixture of air and liquid being supplied to the discharge opening (9). To improve the generation of fine liquid droplets (mist) an outlet of the liquid passage (8) ends into the air passage (13) upstream of the discharge opening (9) to introduce liquid into the air passage and an outlet of the air passage is provided with a nozzle (10) having said discharge opening (9). Preferably the pressurized air and liquid supply is obtained by means of electric pumps (6,7). The liquid may be water or a (diluted) additive liquid.
    Type: Application
    Filed: December 3, 2002
    Publication date: March 31, 2005
    Inventors: Nyik Wong, Yong Jiang, Tao Guo, Kumar Asok S/O Kasevan
  • Publication number: 20050065745
    Abstract: A method of setting a delay offset in slave Delay-Locked Loop (DLL) modules by a master DLL module is disclosed. The method includes determining whether a delay tap value needs to be adjusted based on a comparison with a reference clock signal, calculating a delay offset value to correct the delay tap value, repeating the determining and calculating steps a predetermined number of times and forwarding a representative value of the calculated delay offset values. The representative value is determined through a comparison between all of the calculated delay offset values obtained in the repeating step.
    Type: Application
    Filed: May 14, 2004
    Publication date: March 24, 2005
    Inventor: Yong Jiang
  • Publication number: 20040000519
    Abstract: An improved field-flow fractionation method and apparatus for the separation of sample species 28 contained in a carrier fluid, wherein
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Applicant: Postnova Analytics, Inc.
    Inventors: Yong Jiang, Michael E. Miller, Marcus N. Myers, Andreas M. Kummerow, Soheyl Tadjiki, Marcia E. Hansen, Thorsten Klein
  • Publication number: 20020131456
    Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.
    Type: Application
    Filed: March 18, 2002
    Publication date: September 19, 2002
    Applicant: Broadcom Corporation
    Inventors: Jonathan Lin, Yong Jiang
  • Publication number: 20020133732
    Abstract: A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port.
    Type: Application
    Filed: February 27, 2002
    Publication date: September 19, 2002
    Applicant: Broadcom Corporation
    Inventors: Jonathan Lin, Yong Jiang
  • Patent number: 6192764
    Abstract: Sample focusing method and device for field-flow fractionation techniques that lead to improved detection, improved separation resolution, and a compressed sample plug while permitting a more straightforward quantitation of peaks and reliable large volume injections. The method and device can be implemented in separations that are performed by a variety of field-flow fractionation techniques, including thermal FFF, electrical FFF, sedimentation FFF, gravitational FFF, dielectric FFF, photophoretic FFF, flow FFF, asymmetric flow FFF, and symmetric flow FFF. The sample focusing device can be integrally built into a separation channel or it can be manufactured as an attachable independent piece.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: February 27, 2001
    Assignee: FFFractionation, LLC
    Inventors: Yong Jiang, Marcia E. Hansen, Michael E. Miller, Andreas M. Kummerow
  • Patent number: 6194601
    Abstract: The 5,6-dihydronaphthalenyl derivatives of the formulae possess potent retinoid-like activity against dermatological diseases with a substantially reduced irritancy profile when administered topically.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: February 27, 2001
    Assignee: Bristol-Myers Squibb Company
    Inventors: Anne Marinier, Yong-Jiang Hei, Philippe Lapointe, Jean-Paul Daris
  • Patent number: 6109119
    Abstract: Sample focusing method and device for field-flow fractionation techniques that lead to improved detection, improved separation resolution, and a compressed sample plug while permitting a more straightforward quantitation of peaks and reliable large volume injections. The method and technique can be implemented in separations that are performed by a variety of field-flow fractionation techniques, including thermal FFF, electrical FFF, sedimentation FFF, gravitational FFF, dielectric FFF, photophoretic FFF, flow FFF, asymmetric flow FFF, and symmetric flow FFF. The sample focusing device can be integrally built into a separation channel or it can be manufactured as an attachable independent piece.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: August 29, 2000
    Assignee: FFFractionation, LLC
    Inventors: Yong Jiang, Marcia E. Hansen, Michael E. Miller, Andreas M. Kummerow
  • Patent number: 6010856
    Abstract: Assay systems utilizing a reporter construct based on p38 phosphorylation of myocyte enhancer factor 2 (MEF2) transcription factor are provided. The reporter construct and methods of use are provided, as well as methods of treatment of inflammatory and muscular disorders associated with MEF2-regulated gene expression.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: January 4, 2000
    Assignee: The Scripps Research Institute
    Inventors: Richard J. Ulevitch, Jiahuai Han, Yong Jiang, Zhuang-Jei Li
  • Patent number: 5933385
    Abstract: A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without overwriting the memory addresses for the pending operations. Similarly, data is shifted in the data registers to ensure that data remains available for pending memory access operations. The specific register operations are controlled by a thirteen state state machine. The thirteen states and the relationships between the states are defined to enable the memory controller to perform any combination of read, write and deselect operations without inserting idle cycles.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: August 3, 1999
    Assignee: Integrated Silicon Solution Inc.
    Inventors: Yong Jiang, Ping Lo