Abstract: A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1,

Abstract: A silicon-based hardmask composition, including an organosilane polymer represented by Formula 1: {(SiO1.5—Y—SiO1.5)x(R3SiO1.5)y(XSiO1.5)z}(OH)e(OR6)f??(1).

Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

Abstract: A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1,

Abstract: A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product including about 10 to about 40 mol % of a structural unit represented by Chemical Formula 1:

Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

Abstract: A silicon-based hardmask composition, including an organosilane polymer represented by Formula 1: {(SiO1.5—Y—SiO1.5)x(R3SiO1.5)y(XSiO1.5)z}(OH)e(OR6)f??(1).

Abstract: A resist underlayer composition and a method of manufacturing a semiconductor integrated circuit device, the resist underlayer composition including a solvent and an organosilane-based polymer, the organosilane-based polymer being a polymerization product of at least one first compound represented Chemical Formulae 1 to 3 and at least one second compound represented by Chemical Formulae 4 and 5.