Patents by Inventor Yong-Jin LIOU

Yong-Jin LIOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12293940
    Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Yu-Wen Chen, Yong-Jin Liou, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
  • Publication number: 20240379357
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Patent number: 12100592
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Yong-Jin Liou, Yu-Wen Chen, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
  • Publication number: 20240282582
    Abstract: A method of fabricating a semiconductor device includes determining a concentration of a byproduct in a photoresist composition. A photoresist layer is formed over a substrate using the photoresist composition when the concentration of the byproduct is below a threshold value. A photoresist pattern is formed in the photoresist layer exposing a portion of the substrate, and an operation is performed on the exposed portion of the substrate.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 22, 2024
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20230402315
    Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20230290637
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 14, 2023
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Patent number: 11658031
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Yong-Jin Liou, Yu-Wen Chen, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
  • Publication number: 20220285203
    Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 8, 2022
    Inventors: Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20220285155
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 8, 2022
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU