Patents by Inventor Yong-Jin Yoon

Yong-Jin Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250101587
    Abstract: Disclosed herein is a method of manufacturing a dehydrogenation catalyst, the method includes: forming a functional oxide coating layer on a surface of a support with a first atomic layer deposition; and depositing metal particles on the surface of the support on which the functional oxide coating layer is formed, with a second atomic layer deposition.
    Type: Application
    Filed: June 10, 2024
    Publication date: March 27, 2025
    Inventors: Yong Min KIM, Suk Woo NAM, Hyuntae SOHN, Hyangsoo JEONG, Sung Pil YOON, Sun-Hee CHOI, Yu-Jin LEE
  • Publication number: 20250105370
    Abstract: An embodiment of a flame-retardant electrode includes a flame-retardant layer between an electrode current collector and an electrode active material layer, and an embodiment of an all-solid-state battery including the same, in which the flame-retardant layer includes a flame retardant configured such that the surface of a flame-retardant material is coated with a conductive material, thereby increasing thermal stability and adhesion to the electrode current collector.
    Type: Application
    Filed: March 8, 2024
    Publication date: March 27, 2025
    Inventors: Min Sun Kim, Young Jin Nam, Yeo Min Yoon, Yong Seok Choi, Yong Guk Gwon
  • Publication number: 20250082787
    Abstract: The present invention provides an alginic acid-based injectable hydrogel system for labeling an accurate position of a disease lesion and effectively delivering a drug to a target region. The formulation of the present invention can make it easy to locally inject a contrast agent and a drug into a target region while controlling the release rate of the contrast agent or the drug, with the formation of the hydrogel in the injected region. Through the advantages, the labeled position can be accurately determined from images, thereby enhancing the precision of surgical operation, with a minimal incision formed therefor. In addition, when used, the alginic acid-based injectable hydrogel system allows the effective local delivery of a drug to a target region while increasing the long-acting effect of the drug.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Applicant: National Cancer Center
    Inventors: Yong Doo CHOI, Seon Sook LEE, Hyun Jin KIM, Dae Kyung SOHN, Seok Ki KIM, Young Woo KIM, Keun Won RYU, Hong Man YOON
  • Patent number: 12227688
    Abstract: A liquid-crystal (LC) medium containing one or more dyes and one or more polymerizable compounds, its use for optical, electro-optical and electronic purposes, in particular in LC displays, especially in colour LC displays of the PSA (polymer sustained alignment) or SA (self-aligning) mode containing a quantum dot colour filter (QDCF), an LC display of the PSA or SA mode containing the LC medium and containing a QDCF, and to a process of manufacturing the LC display.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: February 18, 2025
    Assignee: Merck Patent GmbH
    Inventors: Hyun-Woo Bae, Jung-Min Lee, Hyun-Jin Yoon, Yong-Kuk Yun
  • Publication number: 20250034101
    Abstract: Disclosed are oxadiazole compounds and pharmaceutically acceptable salts thereof. The compounds and pharmaceutically acceptable salts thereof are specifically suitable for the treatment of neurological diseases such as epilepsy.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Inventors: Choon Ho RYU, Min Soo HAN, Yeo Jin YOON, Yu Jin KIM, Ka Eun LEE, Ju Young LEE, Myung Jin JUNG, Eun Hee BAEK, Yu Jin SHIN, Eun Ju CHOI, Young Soon KANG, Yong Soo KIM, Yea Mi SONG, Jin Sung KIM, Hee Jeong LIM
  • Patent number: 10637088
    Abstract: Various embodiments may provide a method of forming an energy conversion device. The method may include forming an electrolyte layer on the first surface of the semiconductor substrate. The method may also include forming a cavity on the second surface of the semiconductor substrate using a deep reactive ion etch. The method may further include enlarging said cavity by carrying out one or more wet etches so that the enlarged cavity is at least partially defined by a vertical arrangement comprising a first lateral cavity surface of the semiconductor substrate extending substantially along a first direction, and a second lateral cavity surface of the semiconductor substrate adjoining the first lateral cavity surface. The method may include forming a first electrode on a first surface of the electrolyte layer, and forming a second electrode on a second surface of the electrolyte layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 28, 2020
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Pei-Chen Su, Yong Jin Yoon, Jong Dae Baek
  • Publication number: 20180159162
    Abstract: Various embodiments may provide a method of forming an energy conversion device. The method may include forming an electrolyte layer on the first surface of the semiconductor substrate. The method may also include forming a cavity on the second surface of the semiconductor substrate using a deep reactive ion etch. The method may further include enlarging said cavity by carrying out one or more wet etches so that the enlarged cavity is at least partially defined by a vertical arrangement comprising a first lateral cavity surface of the semiconductor substrate extending substantially along a first direction, and a second lateral cavity surface of the semiconductor substrate adjoining the first lateral cavity surface. The method may include forming a first electrode on a first surface of the electrolyte layer, and forming a second electrode on a second surface of the electrolyte layer.
    Type: Application
    Filed: May 20, 2016
    Publication date: June 7, 2018
    Inventors: Pei-Chen SU, Yong Jin YOON, Jong Dae BAEK
  • Patent number: 8961937
    Abstract: The present invention relates to a composition for detecting beta amyloid aggregates and a composition for diagnosing beta amyloid aggregation disease, comprising a 2-styrilpyridizine-3(2H)-one derivative or its pharmaceutically acceptable salt, to a diagnostic kit for diagnosing beta amyloid aggregation disease comprising said composition and to a method for detecting beta amyloid aggregates using said compositions to provide information for beta amyloid aggregation disease diagnosis.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Korea Atomic Energy Research Institute
    Inventors: Yong Dae Park, Jeong Hoon Park, Yong Jin Yoon, Seung Tae Yang, Min Goo Hur
  • Patent number: 8885394
    Abstract: A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Ho Kang, Yong Jin Yoon, Young Jae Son
  • Publication number: 20140134109
    Abstract: The present invention relates to a composition for detecting beta amyloid aggregates and a composition for diagnosing beta amyloid aggregation disease, comprising a 2-styrilpyridizine-3(2H)-one derivative or its pharmaceutically acceptable salt, to a diagnostic kit for diagnosing beta amyloid aggregation disease comprising said composition and to a method for detecting beta amyloid aggregates using said compositions to provide information for beta amyloid aggregation disease diagnosis.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 15, 2014
    Inventors: Yong Dae PARK, Jeong Hoon PARK, Yong Jin YOON, Seung Tae YANG, Min Goo HUR
  • Patent number: 8643420
    Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Su Kim, Yong-Jin Yoon, Ji-Kyum Kim
  • Patent number: 8578227
    Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jae Son, Yong-Jin Yoon, Uk-Rae Cho
  • Publication number: 20130083592
    Abstract: A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.
    Type: Application
    Filed: September 6, 2012
    Publication date: April 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: BYUNG-HO KANG, YONG JIN YOON, YOUNG JAE SON
  • Publication number: 20120319753
    Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 20, 2012
    Inventors: Min-Su Kim, Yong-Jin Yoon, Ji-Kyum Kim
  • Publication number: 20110154142
    Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.
    Type: Application
    Filed: November 12, 2010
    Publication date: June 23, 2011
    Inventors: Young-Jae SON, Yong-Jin YOON, Uk-Rae CHO
  • Patent number: 7586775
    Abstract: A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-beom Kang, Yong-jin Yoon, Qi Wang
  • Patent number: 7400177
    Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: July 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho
  • Publication number: 20080055964
    Abstract: A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 6, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-beom KANG, Yong-jin YOON, Qi WANG
  • Patent number: 7295489
    Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Jin Yoon, Jong-Cheol Lee, Uk-Rae Cho
  • Publication number: 20070139084
    Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third
    Type: Application
    Filed: January 26, 2007
    Publication date: June 21, 2007
    Inventors: Nam-Seog KIM, Yong-Jin Yoon, Uk-Rae Cho