Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract: A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract: A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.

Abstract: Integrated circuit memory devices having synchronized bit line selection and I/O line precharge capability include an array of memory cells, a pair of differential bit lines electrically coupled to the array of memory cells, a pair of differential input/output lines and a sense amplifier electrically coupled to the pair of differential input/output lines. An equalization circuit is also provided to equalize the potentials of the pair of differential input/output lines in response to a precharge enable signal. A column select circuit is provided to electrically connect the pair of differential bit lines to the pair of differential input/output lines, in response to a column select enable signal. In addition, a control signal generator is provided to generate the column select enable signal and the precharge enable signal during nonoverlapping time intervals and in-sync with an external clock signal. Using these circuits, the timing margins (e.g.

Abstract: A first precharge circuit precharges a bit line to an equalization voltage during precharging operations and is disabled during charge sharing operations floating the bit line. A second precharge circuit precharges a bit line bar to an equalization voltage during precharging and charge sharing operations. Since the bit line is floated during charge sharing operations, and the bit line bar is continually precharged to an equalization voltage level, variation of the bit line bar voltage level due to a charge coupling between the bit line and the bit line bar during charge sharing is prevented. The difference in a level between the bit line and the bit line bar after the charge sharing can be detected by a sense and amplification circuit.

Abstract: A power supply arrangement for a semiconductor chip includes, in a first preferred embodiment, a power supply voltage line, a ground voltage line, an intermediate voltage line, a plurality of first noise reduction capacitors connected between the intermediate voltage line and the power supply voltage line, and a plurality of second noise reduction capacitors connected between the intermediate voltage line and the ground voltage line. In a second preferred embodiment, the power supply arrangement includes a power supply voltage line, a ground voltage line, a quiet power supply voltage line, a quiet ground voltage line, a plurality of first noise reduction capacitors connected between the power supply voltage line and the quiet ground voltage line, and a plurality of second noise reduction capacitors connected between the ground voltage line and the quiet power supply voltage line.