Patents by Inventor Yongjoo Jeon
Yongjoo Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060281240Abstract: A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer without removing a significant amount of the first stressor layer and also planarizing a boundary between the first stressor layer and the second stressor layer.Type: ApplicationFiled: June 9, 2005Publication date: December 14, 2006Inventors: Paul Grudowski, Stanley Filipiak, Yongjoo Jeon, Chad Weintraub
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Patent number: 7074713Abstract: An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.Type: GrantFiled: September 30, 2004Date of Patent: July 11, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Jian Chen, Stanley M. Filipiak, Yongjoo Jeon, Tab A. Stephens
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Patent number: 7041562Abstract: Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.Type: GrantFiled: October 29, 2003Date of Patent: May 9, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Sangwoo Lim, Yongjoo Jeon, Choh-Fei Yeap
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Publication number: 20060073698Abstract: An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Inventors: Jian Chen, Stanley Filipiak, Yongjoo Jeon, Tab Stephens
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Patent number: 6979627Abstract: A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.Type: GrantFiled: April 30, 2004Date of Patent: December 27, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Choh-Fei Yeap, Yongjoo Jeon, Michael D. Turner, Toni D. Van Gompel
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Publication number: 20050242403Abstract: A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) over the first dielectric material in the trench. A third material is deposited in the trench on the second layer. The second material and the third material are selectively etchable with respect to each other. In one example, the first material has a lower dielectric constant than the second material.Type: ApplicationFiled: April 30, 2004Publication date: November 3, 2005Inventors: Choh-Fei Yeap, Yongjoo Jeon, Michael Turner, Toni Van Gompel
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Publication number: 20050156229Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: December 16, 2004Publication date: July 21, 2005Inventors: Geoffrey Yeap, Srinivas Jallepalli, Yongjoo Jeon, James Burnett, Rana Singh, Paul Grudowski
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Publication number: 20050093063Abstract: Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.Type: ApplicationFiled: October 29, 2003Publication date: May 5, 2005Inventors: Sangwoo Lim, Yongjoo Jeon, Choh-Fei Yeap
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Patent number: 6846716Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: GrantFiled: December 16, 2003Date of Patent: January 25, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
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Publication number: 20040124450Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: December 16, 2003Publication date: July 1, 2004Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski
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Patent number: 6753242Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: GrantFiled: March 19, 2002Date of Patent: June 22, 2004Assignee: Motorola, Inc.Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon
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Publication number: 20030181028Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.Type: ApplicationFiled: March 19, 2002Publication date: September 25, 2003Inventors: Geoffrey C-F Yeap, Srinivas Jallepalli, Yongjoo Jeon, James David Burnett, Rana P. Singh, Paul A. Grudowski