Abstract: An operating method of a controller that controls a memory device includes initializing a clock frequency set corresponding to clock signals provided to a plurality of operation modules included in the controller when a change in a current performance or a change in a host request pattern is detected, determining a target performance on the basis of the current performance given after the clock frequency set is initialized, determining an optimal clock frequency set, in which the current performance is able to be maintained equal to or greater than the target performance, by repeatedly performing an operation of changing at least one clock frequency included in the clock frequency set and an operation of monitoring the current performance given after the clock frequency is changed, and providing the plurality of operation modules with clock signals according to the optimal clock frequency set.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may include a plurality of cores, a control core, and a shared memory. When processing the event, the control core may select a first core executing a target job requiring distributed execution among the plurality of cores, and the first core may run a first firmware among the plurality of firmwares to execute the target job. The control core may select a second core to execute the target job together with the first core, and may control the second core to run the first firmware. The control core may control the first core and the second core to perform distributed execution of the target job.

Abstract: Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.

Abstract: Embodiments of the present disclosure relate to a storage system and an operating method thereof. According to the embodiments of the present disclosure, the storage system may include N (N is a natural number) temperature sensors and M (M is a natural number of 2 or more) modules, and may determine a thermal throttling level for each of the M modules based on N temperature information pieces collected from the N temperature sensors and N weights corresponding to the N temperature sensors, wherein the N weights are different for each of the M modules, and the storage system may perform the thermal throttling for the M modules based on the thermal throttling levels for the M modules respectively.

Abstract: Disclosed are a controller and an operating method thereof. According to an embodiment of the present disclosure, a controller that controls a memory device, comprises: a host interface for determining a remaining resource index and outputting a task scheduling instruction when a data throughput determined based on data inputted/outputted between a host and the controller is lower than a maximum throughput required under a current workload pattern; and a processor for: selecting, in response to the task scheduling instruction, at least one of a plurality of internal tasks based on the remaining resource index and resource consumption indexes of the respective internal tasks, and performing the selected internal task while performing an input/output task.

Abstract: An operating method of a controller that controls a memory device includes initializing a clock frequency set corresponding to clock signals provided to a plurality of operation modules included in the controller when a change in a current performance or a change in a host request pattern is detected, determining a target performance on the basis of the current performance given after the clock frequency set is initialized, determining an optimal clock frequency set, in which the current performance is able to be maintained equal to or greater than the target performance, by repeatedly performing an operation of changing at least one clock frequency included in the clock frequency set and an operation of monitoring the current performance given after the clock frequency is changed, and providing the plurality of operation modules with clock signals according to the optimal clock frequency set.

Abstract: An electronic device includes a plurality of cores, and a clock generator configured to provide a plurality of clock signals to the plurality of cores, respectively, wherein the plurality of cores includes a system core that controls the clock generator to generate the clock signals having frequencies of the respective cores, wherein the frequencies are optimized and determined based on a type of an event of the electronic device, and wherein to clock signals with optimized frequencies are applied to the respective cores in order to perform the event.

Abstract: Embodiments of the present disclosure relate to a storage system and an operating method thereof. According to the embodiments of the present disclosure, the storage system may include N (N is a natural number) temperature sensors and M (M is a natural number of 2 or more) modules, and may determine a thermal throttling level for each of the M modules based on N temperature information pieces collected from the N temperature sensors and N weights corresponding to the N temperature sensors, wherein the N weights are different for each of the M modules, and the storage system may perform the thermal throttling for the M modules based on the thermal throttling levels for the M modules respectively.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may include a plurality of cores, a control core and a shared memory, and the control core may, when processing the event, select a first core executing a target job requiring distributed execution among the plurality of cores—the first core runs a first firmware among the plurality of firmwares to execute the target job—may select a second core executing the target job together with the first core, may control the second core to run the first firmware, and may control the first core and the second core to perform distributed execution of the target job.

Abstract: An electronic device includes a plurality of cores, and a clock generator configured to provide a plurality of clock signals to the plurality of cores, respectively, wherein the plurality of cores includes a system core that controls the clock generator to generate the clock signals having frequencies of the respective cores, wherein the frequencies are optimized and determined based on a type of an event of the electronic device, and wherein to clock signals with optimized frequencies are applied to the respective cores in order to perform the event.

Abstract: Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.

Abstract: Disclosed is a cosmetic composition having a double-shell type nano-structure. More particularly, the nano-structure of the cosmetic composition includes: a water-soluble bioactive ingredient core; a core shell containing poly(ethyleneglycol)-poly(caprolactone)-poly(ethyleneglycol) (PE-PCL-PEG) triblock copolymer in order to include the bioactive ingredient core therein; and an outer shell containing phospholipids or derivatives thereof in order to enclose the core shell therein. Such a cosmetic composition improves stability of active components which are prone to oxidation, light degradation, heat degradation, etc., is formed in a nanoparticle size which in turn shows high transdermal absorption and is very useful to prepare a cosmetic composition stably encapsulating various bioactive ingredients with anti-wrinkle effects, whitening effects, and so forth.

Abstract: Disclosed is a cosmetic composition having a double-shell type nano-structure. More particularly, the nano-structure of the cosmetic composition includes: a water-soluble bioactive ingredient core; a core shell containing poly(ethyleneglycol)-poly(caprolactone)-poly(ethyleneglycol) (PE-PCL-PEG) triblock copolymer in order to include the bioactive ingredient core therein; and an outer shell containing phospholipids or derivatives thereof in order to enclose the core shell therein. Such a cosmetic composition improves stability of active components which are prone to oxidation, light degradation, heat degradation, etc., is formed in a nanoparticle size which in turn shows high transdermal absorption and is very useful to prepare a cosmetic composition stably encapsulating various bioactive ingredients with anti-wrinkle effects, whitening effects, and so forth.