Patents by Inventor Yong-June Kim

Yong-June Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8370710
    Abstract: Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jaehong Kim, Junjin Kong
  • Publication number: 20130031443
    Abstract: A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 31, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Chu Oh, Jae-Hong Kim, Yong-June Kim, Jun-Jin Kong
  • Patent number: 8364086
    Abstract: Disclosed are an apparatus and method of determining an optimal cyclic delay value. The method of determining the optimal cyclic delay value includes determining a Signal-to-Interference and Noise Ratio (SINR) function depending on a diversity order; determining a channel estimation error variance function; and determining an SINR being required for a system according to the SINR function and the channel estimation error variance function.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 29, 2013
    Assignees: Electronics and Telecommunications Research Institute, Dongguk University Industry-Academic Cooperation Foundation
    Inventors: Taegyun Noh, Byung Jang Jeong, Hyun Kyu Chung, Dae Woon Lim, Min Joong Lim, Ho Yun Kim, Yong June Kim
  • Publication number: 20130018934
    Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 17, 2013
    Inventors: Yong June Kim, Jung Soo Chung, Jun Jin Kong, Hongrak Son
  • Patent number: 8352808
    Abstract: A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jun Jin Kong, Jae Hong Kim, Kyoung Lae Cho
  • Publication number: 20130007081
    Abstract: A data processing which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 3, 2013
    Inventors: KI JUN LEE, JUN JIN KONG, YONG JUNE KIM, JAE HONG KIM, HONG RAK SON, JUNG SOO CHUNG, SEONG HYEONG CHOI
  • Patent number: 8347194
    Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Seon No, Beom Kyu Shin, Seok Il Youn, Jae Dong Yang, Jun Jin Kong, Jae Hong Kim, Yong June Kim, Kyoung Lae Cho
  • Patent number: 8345487
    Abstract: A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jae Hong Kim, Jun Jin Kong, Hong Rak Son, Seung-Hwan Song
  • Patent number: 8339846
    Abstract: The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-seok Eun, Jong-han Kim, Jae-hong Kim, Dong-hyuk Chae, Seung-hwan Song, Han-woong Yoo, Jun-jin Kong, Young-hwan Lee, Kyoung-lae Cho, Yong-june Kim
  • Patent number: 8316279
    Abstract: A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehong Kim, Yong June Kim, Seung Hwan Song
  • Publication number: 20120290783
    Abstract: A memory device including a randomizer and a memory system including the memory device are provided. The memory device includes: a randomizer including a sequence generator which generates a first sequence from a seed and a converter which converts the first sequence into a second sequence in response to a conversion factor, the randomizer randomizing data to be programmed using the second sequence and outputting the randomized data; and a storage area which receives the randomized data from the randomizer and storing the randomized data.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Soo CHUNG, Yong June KIM, Jun Jin KONG, Hongrak SON
  • Patent number: 8281217
    Abstract: Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jae Hong Kim, Jun Jin Kong
  • Patent number: 8274840
    Abstract: Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-June Kim, Jae-Hong Kim, Kyoung-Lae Cho, Seung-Hwan Song, Jun-Jin Kong
  • Publication number: 20120233518
    Abstract: A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Inventors: Kijun Lee, Junjin Kong, Sejin Lim, Jaehong Kim, Hong-Rak Son, Yong-June Kim
  • Publication number: 20120221775
    Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong June KIM, Hong Rak SON, Jae Hong KIM, Sang Yong YOON, Ki Jun LEE, Jung Soo CHUNG, Seong Hyeog CHOI
  • Publication number: 20120215963
    Abstract: A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period.
    Type: Application
    Filed: November 23, 2011
    Publication date: August 23, 2012
    Inventors: Yong June KIM, Jung Soo CHUNG, Jun Jin KONG, Kyoung Lae CHO
  • Publication number: 20120166708
    Abstract: Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.
    Type: Application
    Filed: September 20, 2011
    Publication date: June 28, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Soo Chung, Yong June Kim, Hong Rak Son, Jun Jin Kong
  • Patent number: 8200607
    Abstract: Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hong Kim, Heeseok Eun, Yong June Kim, Jun Jin Kong, Seung-Hwan Song
  • Patent number: 8179718
    Abstract: Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 15, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Lae Cho, Yoon Dong Park, Jun Jin Kong, Yong June Kim
  • Publication number: 20120069657
    Abstract: A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 22, 2012
    Inventors: Seonghyeog CHOI, Hong Rak Son, Junjin Kong, Jaehong Kim, KyoungLae Cho, Yong June Kim