Abstract: A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and bottom ground planes thermally and electrically bonded together by a number of grounded thermal vias. The top ground plane completely surrounds the wire bond signal connections made with the die, enhancing signal integrity. The top ground plane covers the die mounting area, providing grounding and heat spreading for the die. The thermal vias are also positioned in the mounting area, and thermally couple the die to the bottom-side ground plane. The bottom ground plane is positioned within a central area around which the signal connections from the top-side are arranged. Ground pads with attached solder balls are positioned within the bottom ground plane and conduct heat transferred from the die into a primary circuit board on which the carrier is mounted.

Abstract: A layout of a carrier in an optical component having the carrier and an optical device is described. The layout comprises a pair of terminals, a resistor connected to a first terminal, a wire bond connected in series with the resistor for connecting the resistor to an optical device, and a first ground patch connected to a second terminal and for connecting to an optical device for providing a common ground on a first surface on a substrate on which the carrier is based, whereby the pair of terminals, the resistor, the wire bond and an optical device form an optical signal transmission system in the optical component.

Abstract: A chip scale package assembly comprises an integrated circuit die wire bonded to a carrier for mounting to a printed circuit board. The carrier comprises top and bottom ground planes thermally and electrically bonded together by a number of grounded thermal vias. The top ground plane completely surrounds the wire bond signal connections made with the die, enhancing signal integrity. The top ground plane covers the die mounting area, providing grounding and heat spreading for the die. The thermal vias are also positioned in the mounting area, and thermally couple the die to the bottom-side ground plane. The bottom ground plane is positioned within a central area around which the signal connections from the top-side are arranged. Ground pads with attached solder balls are positioned within the bottom ground plane and conduct heat transferred from the die into a primary circuit board on which the carrier is mounted.

Abstract: A chip scale package (CSP) comprises a flip chip and chip carrier with features to enhance its electrical and thermal performance. The flip chip connects to the chip carrier through alternating signal and ground connections. Top layer routing on the chip carrier substantially maintains ground-based guard isolation between neighboring signal lines. The arrangement of inter-layer vias and bottom layer traces also maintains the isolation for flip chip signals routed to the bottom layer of the chip carrier, where they are available for interconnection with a primary circuit board via solder balls or the like. The bottom layer further includes a centralized ground plane. Special thermal vias extend from the top layer into this bottom layer ground plane. Dedicated solder ball connections for the ground plane provide a ground path between the flip chip and the primary circuit with very low electrical and thermal impedances.

Abstract: The invention relates to a high frequency board-to-board connector for interconnecting electronic sub-assemblies. The high frequency board-to-board connector includes a row of conductive pins received in an insulative housing for connecting with receptacles of a design. Two discrete electronic sub-assemblies, for example PCBs, can be mechanically and electrically connected without the need for a gender male connector on one PCB and a corresponding gender female connector on the other PCB. A plurality of follower arms spaced apart along the grounding plate facilitates contact with a ground plane in the design to form a ground path. The ground path reduces electromagnetic coupling between any pair of conductive pins and consequentially lowering cross-talk noise. Furthermore, inductive parasitics of the conductive pins is reduced, further facilitating high frequency operations.

Abstract: A chip scale package (CSP) comprises a flip chip and chip carrier with features to enhance its electrical and thermal performance. The flip chip connects to the chip carrier through alternating signal and ground connections. Top layer routing on the chip carrier substantially maintains ground-based guard isolation between neighboring signal lines. The arrangement of inter-layer vias and bottom layer traces also maintains the isolation for flip chip signals routed to the bottom layer of the chip carrier, where they are available for interconnection with a primary circuit board via solder balls or the like. The bottom layer further includes a centralized ground plane. Special thermal vias extend from the top layer into this bottom layer ground plane. Dedicated solder ball connections for the ground plane provide a ground path between the flip chip and the primary circuit with very low electrical and thermal impedances.

Abstract: A layout of a carrier in an optical component having the carrier and an optical device is described. The layout comprises a pair of terminals, a resistor connected to a first terminal, a wire bond connected in series with the resistor for connecting the resistor to an optical device, and a first ground patch connected to a second terminal and for connecting to an optical device for providing a common ground on a first surface on a substrate on which the carrier is based, whereby the pair of terminals, the resistor, the wire bond and an optical device form an optical signal transmission system in the optical component.