Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer.

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer.

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

Abstract: Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

Abstract: A testing scheme for ball-grid array devices of different sizes where the same ball-grid pattern may be tested using the same set of test adapters. A testing scheme includes providing a plurality of devices having a predetermined pattern of solder balls attached, providing a plurality of adapters secured to a test board, each of the adapters including a plurality of test contacts arranged in a pattern corresponding to the predetermined pattern of solder balls, removably attaching the plurality of devices to a device holding apparatus such that the predetermined pattern of solder balls on the devices corresponds to the predetermined pattern of test contacts on the plurality of adapters, then positioning the device holding apparatus to bring the plurality of solder balls in contact with the plurality of test contacts.

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

Abstract: The present invention provides systems and methods which overcome the shortcomings of the prior art by providing a testing scheme wherein ball-grid array devices of different sizes but the same ball-grid pattern may be efficiently and cost-effectively tested using the same set of test adapters.

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.

Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.