Abstract: The present disclosure relates to the technical field of drilling, in particular to a composite material, a composition, a drilling fluid, and a method for plugging formation well wall fractures. The composite material includes a polymer matrix and metal ions embedded in the polymer matrix, an embedding rate of the metal ions is not less than 90 wt %, and turbidity of an aqueous solution of the composite material is not less than 1000 NTU under a condition of pH?8. The composite material can actively and quickly identify a change in a formation environment based on a difference in pH values between the drilling fluid and the formation environment, and achieve a precise response and precise matching with a formation well wall fracture environment, and a small amount of composite material can effectively increase a plugging rate of the formation well wall fracture.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

Abstract: Provided in the present invention are an anti-human thymic stromal lymphopoietin (TSLP) monoclonal antibody and the use thereof. The monoclonal antibody has high affinity for human TSLP, has a neutralizing activity, and can be used for preventing or treating TSLP-mediated diseases.

Abstract: Disclosed by the present invention are an anti-human interleukin 17A monoclonal antibody and an application thereof. The epitope of the monoclonal antibody binding to human interleukin 17A comprises 78th asparagine (N78). The antibody may be used to treat rheumatoid arthritis, psoriasis, multiple sclerosis, psoriatic arthritis, plaque psoriasis and/or ankylosing spondylitis.

Abstract: Provided in the present application are an anti-human interleukin-33 monoclonal antibody and the use thereof. The monoclonal antibody has a high affinity for human interleukin-33, has neutralizing activity, and can be used for preventing or treating related diseases mediated by human interleukin-33.

Abstract: Provided are an anti-human interferon ? receptor 1 (IFNAR1) monoclonal antibody and an application thereof. Compared with anti-human IFNAR1 monoclonal antibody Anifrolumab, the anti-human (IFNAR1) monoclonal antibody of the present application has a similar binding affinity to human IFNAR1, and the neutralizing activity thereof at the cellular level is comparable to that of Anifrolumab. In addition, the present application is expected to be used for the prevention and treatment of related diseases.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

Abstract: An apparatus for an artificial intelligence neural network based on co-evolving neural ordinary differential equations (NODEs) includes a main NODE module configured to provide a downstream machine learning task; and an attention NODE module configured to receive the downstream machine learning task and provide attention to the main NODE module, in which the main NODE module and the attention NODE module may influence each other over time so that the main NODE module outputs a multivariate time-series value at a given time for an input sample x.

Abstract: Configuration of signal strength calibration offset is provided. A user interface is displayed, to a screen of a mobile device, for configuration of a signal strength offset of a wireless transceiver to a vehicle, the signal strength offset being an offset with respect to a default calibration of signal strength measurements between the wireless transceiver and the vehicle, the signal strength calibration being for use in calibrating a location of the mobile device for a passive zone with respect to the vehicle. An update to the signal strength calibration is received from the user interface. The signal strength calibration as updated is sent to the vehicle for use in locating the mobile device for the passive zone.

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region with an etch stop layer interposed therebetween, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

Abstract: Disclosed by the present invention are an anti-human interleukin 17A monoclonal antibody and an application thereof. The epitope of the monoclonal antibody binding to human interleukin 17A comprises 78th asparagine (N78). The antibody may be used to treat rheumatoid arthritis, psoriasis, multiple sclerosis, psoriatic arthritis, plaque psoriasis and/or ankylosing spondylitis.

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer, and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first inter layer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second inter layer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.

Abstract: A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate, forming an insulating pattern layer on the lower interconnect through self-assembly, forming an interlayer insulating layer and a trench mask on the insulating pattern layer, forming a preparatory via hole allowing the insulating pattern layer to be exposed by removing a portion of the interlayer insulating layer, forming a trench by etching the interlayer insulating layer using the trench mask, forming a via hole allowing the lower interconnect to be exposed by selectively etching the insulating pattern layer within the preparatory via hole, and filling the trench and the via hole with an conductive material.

Abstract: In a method of manufacturing a semiconductor device, a first insulating interlayer and a sacrificial layer is sequentially formed on a substrate. The sacrificial layer is partially removed to form a first opening exposing an upper surface of the first insulating interlayer. An insulating liner including silicon oxide is conformally formed on the exposed upper surface of the first insulating interlayer and a sidewall of the first opening. At least a portion of the insulating liner on the upper surface of the first insulating interlayer and a portion of the first insulating interlayer thereunder are removed to form a second opening connected to the first opening. A self-forming barrier (SFB) pattern is formed on a sidewall of the second opening and the insulating liner. A wiring structure is formed to fill the first and second openings. After the sacrificial layer is removed, a second insulating interlayer is formed.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.