Patents by Inventor Yong Kong Siew

Yong Kong Siew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7993997
    Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: August 9, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
  • Patent number: 7947604
    Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: May 24, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Fan Zhang, Lup San Leong, Yong Kong Siew, Bei Chao Zhang
  • Patent number: 7833900
    Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: November 16, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Lup San Leong, Yong Kong Siew, Liang Choo Hsia
  • Patent number: 7670946
    Abstract: A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch (e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: March 2, 2010
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yong Kong Siew, Beichao Zhang
  • Publication number: 20090315115
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 24, 2009
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Beichao Zhang, Johnny Widodo, Juan Boon Tan, Yong Kong Siew, Fan Zhang, Haifeng Sheng, Wenhe Lin, Young Way Teh, Jinping Liu, Vincent Ho, Liang Choo Hsia
  • Publication number: 20090233441
    Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Lup San Leong, Yong Kong Siew, Liang Choo Hsia
  • Publication number: 20090191792
    Abstract: The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Fan ZHANG, Lup San LEONG, Yong Kong SIEW, Bei Chao ZHANG
  • Patent number: 7524755
    Abstract: A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: April 28, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Johnny Widodo, Bei Chao Zhang, Tong Qing Chen, Yong Kong Siew, Fan Zhang, San Leong Liew, John Sudijono, Liang Choo Hsia
  • Publication number: 20090085122
    Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 2, 2009
    Inventors: Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang, Fan Zhang, Haifeng Sheng, Juan Boon Tan
  • Patent number: 7247555
    Abstract: A method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation. Via first patterning in dual damascene processing is one of the major integration schemes for copper backend of line (BEOL) integration. Via first dual damascene scheme usually uses a hard mask layer deposited on top of an inter-metal dielectric (IMD) film stack. The dual damascene trench etch requires uniform trench depth across wafer after etch. In addition, via top corner profiles need to be well maintained without any fencing or faceting. The present method solves these problems by using a two component hard mask layer, termed a bi-layer, deposited directly on top of an inter-metal dielectric (IMD) film stack.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: July 24, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Hai Cong, Yong Kong Siew, Liang Choo Hsia
  • Patent number: 6406975
    Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 18, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Victor Seng Keong Lim, Young-Way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6380106
    Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: April 30, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Seng Keong Victor Lim, Young-way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6121135
    Abstract: A new method of forming a butted contact and a buried contact having low contact resistance in the fabrication of integrated circuits is described. A first layer of polysilicon is deposited over a gate silicon oxide layer over the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away to provide an opening to the substrate. A second polysilicon layer is deposited over the first polysilicon layer and the substrate within the opening and doped whereby the buried contact junction is formed in the substrate underlying the doped second polysilicon layer. The second polysilicon layer is planarized. The first and second polysilicon layers are etched away to provide an opening overlying a portion of the buried contact junction wherein a trench is etched into the substrate where the substrate is not covered by the gate oxide layer. An oxide layer is deposited over the second polysilicon layer and within the trench.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: September 19, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Kong Siew, Lap Chan