Patents by Inventor Yong Kong

Yong Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040130537
    Abstract: A method for driving a touch panel that detects and compensates a double touch includes sequentially inputting coordinate values of touched points on the touch panel at predetermined time intervals, measuring a variation of the inputted coordinate values, determining the inputted coordinate values as a double touch when the measured variation is greater than a predetermined value, and compensating the inputted coordinate values if determined as a double touch.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 8, 2004
    Applicant: LG.PHILIPS LCD CO., LTD.
    Inventors: Nam Yong Kong, Cheon Suck Lee
  • Publication number: 20040104899
    Abstract: A touch panel for a display device integrates functionality provided by resistive-type and EM-type touch panels. The touch panel is integrated with the display device and includes a resisitve-type touch panel arranged above the display device and an EM-type touch panel arranged below the display device.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 3, 2004
    Inventors: Hee Jung Hong, Nam Yong Kong, Tae Ho You, Hee Jeong Park, Cheon Suck Lee
  • Patent number: 6602801
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: August 5, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Siew Yong Kong, Alex See, Simon Chooi, Gautam Sarkar
  • Patent number: 6600863
    Abstract: An alloy-coated optical fiber and a fabricating method. In the alloy-coated optical fiber, a core is formed of a light transmitting material, a clad surrounds the outer circumferential surface of the core, and an indium-tin-silver coating layer is formed around the outer circumferential surface of the clad while maintaining the alloy temperature at substantially 5° C. above the melting point of this indium-silver alloy coat.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: July 29, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Un-Chul Paek, Dong-Soo Park, Yong-Kong Seo, Jin-Han Kim
  • Publication number: 20030092251
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Soo Choi Pheng, Lap Chan, Wang Cui Yang, Siew Yong Kong, Alex See
  • Publication number: 20030092240
    Abstract: A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Siew Yong Kong, Alex See, Simon Chooi, Gautam Sarkar
  • Patent number: 6406975
    Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 18, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Victor Seng Keong Lim, Young-Way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6380106
    Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: April 30, 2002
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Seng Keong Victor Lim, Young-way Teh, Ting-Cheong Ang, Alex See, Yong Kong Siew
  • Patent number: 6121135
    Abstract: A new method of forming a butted contact and a buried contact having low contact resistance in the fabrication of integrated circuits is described. A first layer of polysilicon is deposited over a gate silicon oxide layer over the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away to provide an opening to the substrate. A second polysilicon layer is deposited over the first polysilicon layer and the substrate within the opening and doped whereby the buried contact junction is formed in the substrate underlying the doped second polysilicon layer. The second polysilicon layer is planarized. The first and second polysilicon layers are etched away to provide an opening overlying a portion of the buried contact junction wherein a trench is etched into the substrate where the substrate is not covered by the gate oxide layer. An oxide layer is deposited over the second polysilicon layer and within the trench.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: September 19, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Kong Siew, Lap Chan