Patents by Inventor Yong-Kwan Lee

Yong-Kwan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040127
    Abstract: A method of fabricating a semiconductor device. A cell area and a core area are defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.
    Type: Application
    Filed: October 9, 2024
    Publication date: January 30, 2025
    Inventors: JIN A KIM, SUN YOUNG LEE, YONG KWAN KIM, JI YOUNG KIM, CHANG HYUN CHO
  • Publication number: 20250030369
    Abstract: A motor driving apparatus includes a motor having a plurality of windings, a dual inverter including a first inverter connected to first ends of the plurality of windings and a second inverter connected to second ends of the plurality of windings and configured to drive the motor through at least one of the first inverter or the second inverter according to a motor driving mode, and a controller configured to determine whether flux weakening control is performed according to an available voltage level of the dual inverter when a switching condition of the motor driving mode is satisfied and to perform the flux weakening control by linearly adjusting an output voltage level of the dual inverter for a preset time interval for which the flux weakening control is performed.
    Type: Application
    Filed: November 17, 2023
    Publication date: January 23, 2025
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Young Ho CHAE, Young Kwan KO, Hyun Jae LIM, Young Gi LEE, Joo Young PARK, Yong Jae LEE
  • Patent number: 12051680
    Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: July 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Hwan Kim, Hyung Gil Baek, Young-Ja Kim, Kang Gyune Lee, Sang-Won Lee, Yong Kwan Lee
  • Publication number: 20240145268
    Abstract: A molding apparatus for fabricating a semiconductor package includes an upper mold including an upper cavity, a first side cavity at a first side of the upper cavity, a second side cavity formed at an opposite second side of the upper cavity, and a first driving part connected to the first side cavity and configured to move the first side cavity in a first direction, and a bottom mold including a bottom cavity configured to receive a molding target including a package substrate and at least one semiconductor chip. A width in the first direction between the first side cavity and the second side cavity may be smaller than a width of the package substrate in the first direction and greater than a width in the first direction between a first boundary and a second boundary of the at least one semiconductor chip.
    Type: Application
    Filed: September 15, 2023
    Publication date: May 2, 2024
    Inventors: Jun Woo Park, Gyu Hyeong Kim, Seung Hwan Kim, Jung Joo Kim, Jong Wan Kim, Yong Kwan Lee
  • Patent number: 11955359
    Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Young Oh, Seung Hwan Kim, Jong Ho Park, Yong Kwan Lee, Jong Ho Lee
  • Patent number: 11862570
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Patent number: 11699626
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Oh, Hyun-ki Kim, Sang-soo Kim, Seung-hwan Kim, Yong-kwan Lee
  • Publication number: 20230120252
    Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.
    Type: Application
    Filed: May 3, 2022
    Publication date: April 20, 2023
    Inventors: TAE HWAN KIM, HYUNG GIL BAEK, YOUNG-JA KIM, KANG GYUNE LEE, SANG-WON LEE, YONG KWAN LEE
  • Patent number: 11562965
    Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Sang Soo Kim, Yong Kwan Lee, Hyun Ki Kim, Seok Geun Ahn, Jun Young Oh
  • Publication number: 20220392845
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 8, 2022
    Inventors: Jung Joo KIM, Sun Chul KIM, Min Keun KWAK, Hyun Ki KIM, Hyung Gil BAEK, Yong Kwan LEE
  • Patent number: 11450614
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Publication number: 20210391199
    Abstract: The present disclosure provides a magazine supporting equipment for supporting a magazine with multiple input ports. The magazine supporting equipment comprises a contact plate, a first sidewall plate, and a second sidewall plate. The contact plate is in contact with the magazine. The first sidewall plate extends vertically from one end of the contact plate. The second sidewall plate parallel is to the first sidewall plate and extends vertically from one end to the other end of the contact plate. The first sidewall plate extends along at least a part of a first sidewall of the magazine. The second sidewall plate extends along at least a part of a second sidewall of the magazine. The first sidewall plate and the second sidewall plate include control openings through which gas flows in and out.
    Type: Application
    Filed: March 15, 2021
    Publication date: December 16, 2021
    Inventors: Jun Young OH, Seung Hwan KIM, Jong Ho PARK, Yong Kwan LEE, Jong Ho LEE
  • Publication number: 20210366834
    Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 25, 2021
    Inventors: Sun Chul Kim, Sang Soo Kim, Yong Kwan Lee, Hyun Ki Kim, Seok Geun Ahn, Jun Young Oh
  • Publication number: 20210320067
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Application
    Filed: September 28, 2020
    Publication date: October 14, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung Joo KIM, Sun Chul KIM, Min Keun KWAK, Hyun Ki KIM, Hyung Gil BAEK, Yong Kwan LEE
  • Publication number: 20210320043
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-young OH, Hyun-ki KIM, Sang-soo KIM, Seung-hwan KIM, Yong-kwan LEE
  • Patent number: 11069588
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Oh, Hyun-ki Kim, Sang-soo Kim, Seung-hwan Kim, Yong-kwan Lee
  • Patent number: 10756075
    Abstract: A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Gi Hong, Yong Kwan Lee
  • Patent number: 10607905
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Publication number: 20200043820
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.
    Type: Application
    Filed: March 19, 2019
    Publication date: February 6, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-young OH, Hyun-ki KIM, Sang-soo KIM, Seung-hwan KIM, Yong-kwan LEE
  • Publication number: 20190363073
    Abstract: A semiconductor device package-on-package (PoP) includes a first package, a second package, an interposer, a first molding layer, and a second molding layer. The first package includes a first substrate and a first semiconductor chip on the first substrate. The second package is disposed on the first package and includes a second substrate and a second semiconductor chip on the second substrate. The interposer is disposed between the first package and the second package and connects the first package and the second package. A first molding layer fills a space between the first package and the interposer. A second molding layer covers an upper surface of the interposer.
    Type: Application
    Filed: October 22, 2018
    Publication date: November 28, 2019
    Inventors: Min Gi HONG, Yong Kwan LEE