Patents by Inventor Yong Kyoo Choi

Yong Kyoo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118036
    Abstract: A vapor chamber comprises a front surface member having a curvature, a rear surface member coupled to the front surface member, a wick disposed between the front surface member and the rear surface member, and a refrigerant at least partially filled between the front surface member and the rear surface member, wherein the rear surface member includes a plurality of bent areas.
    Type: Application
    Filed: July 20, 2023
    Publication date: April 11, 2024
    Applicant: Samsung Display Co., LTD.
    Inventors: Wee Joon JEONG, Yong Il KIM, Byoung Kyoo PARK, Jang Un CHOI
  • Patent number: 7977016
    Abstract: A method for fabricating an extreme ultraviolet (EUV) lithography mask comprises forming a reflecting layer, an absorber layer, and a resist layer over a substrate; defining a plurality of split regions by partially splitting the resist layer with regular spacing; performing an exposure process, wherein the exposure region is irradiated with an electron beam at different intensities on the split regions to generate a difference in electron beam doses implanted into the resist layer; forming a resist layer pattern which selectively exposes the absorber layer and has a slanted side wall profile by performing a development process to remove a portion of the resist layer, into which the electron beam doses are implanted; and forming an absorber layer pattern with a slanted side wall profile by sequentially etching the portion of the absorber layer exposed by the resist layer pattern.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 12, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi
  • Patent number: 7764368
    Abstract: Provided are a method and apparatus for inspecting mask defects. The method may include preparing a mask with a defect inspecting pattern, formed on a transparent substrate. The method may further include preparing a wafer defect inspecting apparatus including a defect inspecting unit capable of detecting defects through radiating light on a surface of a mask and obtaining an image based on reflected light, and a mask stage on which the mask is mounted facing the defect inspecting unit. The mask stage may replace the wafer stage of a wafer defect inspecting apparatus, and the mask stage may support the mask at a surface height substantially equal to a surface height of the wafer mounted on the wafer stage. The method may also include mounting the mask on the mask stage and detecting mask defects through operating the defect inspecting unit to radiate light on a surface of the mask and obtain an image based on reflected light.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: July 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi, Byung Sup Cho
  • Publication number: 20090317728
    Abstract: A method for fabricating an extreme ultraviolet (EUV) lithography mask comprises forming a reflecting layer, an absorber layer, and a resist layer over a substrate; defining a plurality of split regions by partially splitting the resist layer with regular spacing; performing an exposure process, wherein the exposure region is irradiated with an electron beam at different intensities on the split regions to generate a difference in electron beam doses implanted into the resist layer; forming a resist layer pattern which selectively exposes the absorber layer and has a slanted side wall profile by performing a development process to remove a portion of the resist layer, into which the electron beam doses are implanted; and forming an absorber layer pattern with a slanted side wall profile by sequentially etching the portion of the absorber layer exposed by the resist layer pattern.
    Type: Application
    Filed: December 31, 2008
    Publication date: December 24, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi
  • Publication number: 20080186497
    Abstract: Provided are a method and apparatus for inspecting mask defects. The method may include preparing a mask with a defect inspecting pattern, formed on a transparent substrate. The method may further include preparing a wafer defect inspecting apparatus including a defect inspecting unit capable of detecting defects through radiating light on a surface of a mask and obtaining an image based on reflected light, and a mask stage on which the mask is mounted facing the defect inspecting unit. The mask stage may replace the wafer stage of a wafer defect inspecting apparatus, and the mask stage may support the mask at a surface height substantially equal to a surface height of the wafer mounted on the wafer stage. The method may also include mounting the mask on the mask stage and detecting mask defects through operating the defect inspecting unit to radiate light on a surface of the mask and obtain an image based on reflected light.
    Type: Application
    Filed: December 27, 2007
    Publication date: August 7, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Hyun Oh, Yong Kyoo Choi, Byung Sup Cho
  • Patent number: 6242164
    Abstract: Disclosed is a method for patterning a chemical amplified photoresist which improves resolution by adjusting a diffusion direction of photo acid. The method for patterning a chemical amplified photoresist includes the steps of depositing a chemical amplified photoresist on an etching target layer, selectively exposing the chemical amplified photoresist to generate photo acid on a surface of the exposed chemical amplified photoresist, diffusing the photo acid in only one direction by performing PEB process on condition that electric field is applied to the chemical amplified photoresist, and patterning the chemical amplified photoresist by developing process to remove only a portion where the photo acid is diffused.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: June 5, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Yong Kyoo Choi, Byeong Chan Kim
  • Patent number: 6214498
    Abstract: The present invention relates to a lithography mask and a fabricating method thereof, more particularly, to a mask or an aperture for lithography using electron or ion beams in a semiconductor device and a fabricating method thereof which improve thermal stability of a mask by forming a stencil mask of double structures comprised of an upper mask that absorbs and releases most of electron energy and a lower mask that defines patterns with electron/ion beams, thereby improving the reliance of fine patterns on an exposure process.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: April 10, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Yong-Kyoo Choi
  • Patent number: 6168907
    Abstract: A method for etching a semiconductor device suitable for forming micron contact hole having a size of less than limit resolution power of exposure equipments is disclosed, including coating a layer for an etch mask on an etched object layer; selectively patterning the layer to form an open area; and swelling side part of the patterned layer and forming the etch mask.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: January 2, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Yong Kyoo Choi, Byeong Chan Kim
  • Patent number: 6080514
    Abstract: A fabrication method of a mask for a semiconductor device includes the steps of: applying a first photoresist film on a silicone wafer; sequentially stacking a first insulation film, a second insulation film, and a second photoresist film on the first photoresist film; patterning the second photoresist film by an etching process; etching and patterning the first and second insulation films by using the patterned second photoresist film as a mask; etching and patterning the first photoresist film by using the patterned first and second insulation films, and patterned second photoresist film as a mask; removing the second photoresist film; etching a predetermined portion of the patterned first insulation film; depositing a metal on the wafer including the first photoresist film, the first insulation film having the predetermined etched portion, and the second insulation film; and removing the first photoresist film, and first and second insulation films from the wafer.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: June 27, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventor: Yong-Kyoo Choi
  • Patent number: 5891596
    Abstract: A method for fabricating a phase shifting mask includes the steps of: forming a light shielding layer on a light transmitting substrate; forming a first mask on the light shielding layer; forming plural openings in the light shielding layer through to the substrate by patterning the light shielding layer using the first mask; forming a second mask layer on the light transmitting substrate and on the first mask layer pattern; patterning the second mask layer to form a second mask that exposes selected ones of the openings in the light shielding layer; and forming a phase shifting region in the light transmitting substrate using the first and second masks. The method prevents the light shielding layer from being damaged by the etching process that forms the phase shifting region, and makes it possible to transfer a pattern accurately, thus achieving a phase shifting mask having high reliability.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: April 6, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Yong Kyoo Choi
  • Patent number: 5824438
    Abstract: The structure of a phase shift mask and a method of manufacturing the same are disclosed. A phase shifting mask in accordance with the present invention comprises a light transmitting substrate, a phase shifting layer formed on the upper side of the light transmitting substrate, an adhesive layer formed on the phase shifting layer, and a light shielding layer formed on the adhesive layer. Accordingly, when etching the phase shifting layer, the light shielding layer is protected by the adhesive layer. The adhesive strength is increased due to the adhesive layer formed between the phase shifting layer and the light shielding layer, thereby much improving the reliability of the phase shifting mask.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: October 20, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventors: Yong-Kyoo Choi, Chan-Min Park, Jun-Seok Lee
  • Patent number: 5770336
    Abstract: A lithography mask and a method for fabricating a mask are disclosed. The method includes the steps of forming a plurality of insulating film patterns on a semiconductor substrate, forming a plurality of doped regions in the semiconductor substrate, forming a conductive layer on the doped regions and the insulating film patterns, and forming a plurality of passages through the semiconductor substrate. The lithography mask includes a semiconductor substrate, a plurality of patterns formed on the semiconductor substrate, a plurality of doped regions formed in the semiconductor substrate between the patterns, a plurality of trenches formed on a lower portion of the semiconductor substrate to expose the doped regions, and a plurality of first holes each penetrating a corresponding one of the doped regions.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 23, 1998
    Assignee: LG Semicon Co., Ltd
    Inventor: Yong-Kyoo Choi
  • Patent number: 5658695
    Abstract: A method is provided for fabricating a phase shift mask of the out rigger sub-resolution type capable of accurately fabricating an ultra-fine semiconductor circuit.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: August 19, 1997
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Yong Kyoo Choi
  • Patent number: 5650347
    Abstract: A method of manufacturing a lightly doped drain MOS transistor having the double shallow junction is disclosed including the steps of forming a gate and a gate insulating film on a semiconductor substrate of a first conductivity type, sequentially; forming, on the top and sidewalls of the gate, on side edges of the gate insulating layer, and on the substrate, an insulating film including two kinds of impurities whose diffusivity and conductivity type are different from each other forming a cap insulating film on the insulating film; performing the heat treatment process thereby to form impurity regions of a second conductivity type and impurity regions of the first conductivity type surrounding the impurity regions of the second conductivity type, on both sides of the gate in the substrate; etching the insulating film and the cap insulating film thereby to form sidewall spacers on both sides of the gate; and ion-implanting an impurity of the second conductivity type in the substrate thereby to form impurity r
    Type: Grant
    Filed: July 26, 1995
    Date of Patent: July 22, 1997
    Assignee: LG Semicon Co., Ltd.
    Inventor: Yong-Kyoo Choi